DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/9/2026.
Examiner Note
Claim 1 has been amended to recite a bonding layer, a current-blocking layer and an adhesion layer which are only part of elected Species B (Fig. 4). Withdrawn claims 10-14 only read on non-elected Species C (Fig. 5) and do not include a bonding layer, a current-blocking layer nor an adhesion layer. Claims 10-14 would not be eligible for rejoinder since they combine elements of two different species into an unsupported new embodiment.
Claim Rejections –35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (US 20030141506 A1) in view of Sung et al. (US 20190051797 A1).
Regarding claim 1, Sano discloses a light emitting diode (Fig. 12F), comprising:
an epitaxial structure (2, [0110]) having a first surface (top) and a second surface (bottom) opposite to each other, wherein the epitaxial structure sequentially comprises a first-type semiconductor layer (2c), an active layer (2b), and a second-type semiconductor layer (2a) in a direction (top to bottom) from the first surface to the second surface,
a first electrode (6) electrically connected to the first-type semiconductor layer (2c) and at least comprising a first pad electrode (left of 6) and a first extended electrode (right of 6); and
an insulating layer (7) located above an exposed mesa of the first-type semiconductor layer (2c) and the second-type semiconductor layer (2a), wherein the insulating layer is provided with a first via (see below; a via is an opening per MPEP 2111) penetrating through the insulating layer, the first pad electrode (left of 6) is disposed in (at least from a top down perspective) the first via and is electrically connected to the first-type semiconductor layer (2c), the insulating layer is further provided with a second via (see below; a via is an opening per MPEP 2111), and the first extended electrode (right of 6) is disposed in (at least from a top down perspective) the second via and is electrically connected to the first-type semiconductor layer (2c),
wherein a bonding layer (13; MPEP 2111) is disposed (indirectly) on a (bottom) side of the second-type semiconductor layer (2a) away from the active layer (2b), a substrate (11) is connected to the second-type semiconductor layer (2a) through (at least indirectly) the bonding layer (13), and a current-blocking layer (4b; MPEP 2111) is further disposed between the second-type semiconductor layer (2a) and the bonding layer (13),
wherein an adhesion layer (4a; MPEP 2111) is disposed on one (bottom) side of the current-blocking layer (4b), the current-blocking layer (4b) is located between the adhesion layer (4a) and the second-type semiconductor layer (2a), and the adhesion layer (4a) is a transparent oxide layer ([0029] SiO2).
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Sano fails to disclose wherein an upper surface and a sidewall of the first pad electrode are covered with a first metal covering layer, the first metal covering layer is provided with a first bump at a bottom portion of the sidewall of the first pad electrode, the first bump is located below the insulating layer and contacts the first-type semiconductor layer, the first metal covering layer is made of and inert conductive metal.
Sung discloses wherein an upper surface and a sidewall of the first pad electrode (161) are covered with a first metal covering layer (162), the first metal covering layer is provided with a first bump (see below) at a bottom portion of the sidewall of the first pad electrode, the first bump is located below the insulating layer (172) and contacts the first-type semiconductor layer (123), the first metal covering layer is made of an inert conductive metal ([0058] discloses inert metals, e.g., Rh).
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It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the metal covering layer and associated structures of Sung into Sano and arrive at the claimed inventio so as to improve current injection efficiency per [0073] of Sung.
Note: the modification of Sano by Sung provides for a metal covering layer in both the first pad electrode and the first extended electrode of Sano since Sano discloses said electrodes and Sung provides a motivation for adding metal coverings to said electrodes.
Regarding claim 2, Sano/Sung discloses the light emitting diode according claim 1, wherein an upper surface and a sidewall of the first extended electrode (similar to 161) are covered with a second metal covering layer (similar to 162), the second metal covering layer is provided with a second bump (similar to bump above) at a bottom portion of the sidewall of the first extended electrode, the second bump is located below the insulating layer (172) and contacts the first-type semiconductor layer (123), and the second metal covering layer is made of the inert conductive metal ([0058] discloses inert metals, e.g., Rh. As stated above, the modification of Sano by Sung provides for a metal covering layer in both the first pad electrode and the first extended electrode of Sano since Sano discloses said electrodes and Sung provides a motivation for adding metal coverings to said electrodes).
Regarding claim 3, Sano/Sung discloses the light emitting diode according claim 1, wherein a material of each of the first metal covering layer (162) and a second metal covering layer (similar to 162 duplicated on both the first pad electrode and the first extended electrode of Sano) is at least one of Au, Pt, or Ti ([0058], Ti disclosed. As stated above, the modification of Sano by Sung provides for a metal covering layer in both the first pad electrode and the first extended electrode of Sano since Sano discloses said electrodes and Sung provides a motivation for adding metal coverings to said electrodes).
Regarding claim 4, Sano/Sung fails to disclose the light emitting diode according claim 1, wherein a thickness of each of the first metal covering layer and a second metal covering layer is 10A to 1,000A (recall, the modification of Sano by Sung provides for a metal covering layer in both the first pad electrode and the first extended electrode of Sano since Sano discloses said electrodes and Sung provides a motivation for adding metal coverings to said electrodes).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select a thickness within the claimed range in Sano/Sung so as to improve current injection efficiency per [0073] of Sung and/or prevent corrosion of the electrodes per [0058] of Sung while minimizing the vertical footprint of the device.
Regarding claim 9, Sano/Sung discloses the light emitting diode according claim 1, wherein the light emitting diode has a vertical structure (Fig. 12F) or a flip-chip structure.
Regarding claim 17, Sano/Sung discloses the light emitting diode according claim 1, wherein a mirror layer (Reflecting layer) is disposed between the bonding layer (13) and the current-blocking layer (4b, Fig. 12F).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (US 20030141506 A1) in view of Sung et al. (US 20190051797 A1) as applied to claims 1 and 2 above, and further in view of Ozawa et al. (JP 2008171884 A).
Regarding claim 5, Sano/Sung fails to disclose the light emitting diode according claim 1, wherein a distance between the first bump and a surface of the bottom portion of the sidewall of the first pad electrode is 0.5um to 5um, and a thickness of the first bump is less than 1,000A.,
Ozawa discloses wherein a distance (X) between the first bump (of 22) and a surface of the bottom portion of the sidewall of the first pad electrode (21) is greater than 0um
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It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the bump dimensions of Ozawa into Sano/Sung including the claimed distance as “0.5um to 5um” and thereby arrive at the claimed invention so as to restrict diffusion of metal atoms of the underlying metal electrode per Ozawa (“a titanium (Ti) layer having a thickness of 10 nm between the gold contact layer and the p-contact electrode 21 made of a silver alloy also functions as a barrier layer for preventing silver migration”) and ensure the underlying metal electrode is fully passivated/protected.
Regarding claim 6, Sano/Sung fails to disclose the light emitting diode according claim 2, wherein a distance between the second bump and a surface of the bottom portion of the sidewall of the first extended electrode is 0.5um to 5um, and a thickness of the second bump is less than 1,000A.
Ozawa discloses wherein a distance (X) between the second bump (of 22) and a surface of the bottom portion of the sidewall of the first extended electrode (21) is greater than 0um
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It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the bump dimensions of Ozawa into Sano/Sung including the claimed distance as “0.5um to 5um” and thereby arrive at the claimed invention so as to restrict diffusion of metal atoms of the underlying metal electrode per Ozawa (“a titanium (Ti) layer having a thickness of 10 nm between the gold contact layer and the p-contact electrode 21 made of a silver alloy also functions as a barrier layer for preventing silver migration”) and ensure the underlying metal electrode is fully passivated/protected.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (US 20030141506 A1) in view of Sung et al. (US 20190051797 A1) as applied to claim 1 above, and further in view of Shakuda (US 20090256170 A1).
Regarding claim 7, Sano/Sung fails to disclose the light emitting diode according claim 1, wherein an ohmic contact layer is disposed in the second via, and the first extended electrode is electrically connected to the first-type semiconductor layer through the ohmic contact layer.
Shakuda discloses wherein an ohmic contact layer (61) is disposed in the second via (of 7), and the first extended electrode (as 62) is electrically connected to the first-type semiconductor layer (as 4) through the ohmic contact layer (Fig. 1, [0047]- “Further, the Au layer 61 of the p-side electrode 6 can easily form an ohmic contact with the p-GaN layer 4. This is also advantageous for reducing the drive voltage of the semiconductor light emitting element A”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the ohmic contact layer of Shakuda in Sano/Sung so as to reduce driving voltage of an LED per Shakuda at [0047].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (US 20030141506 A1) in view of Sung et al. (US 20190051797 A1) as applied to claim 1 above, and further in view of Choi et al. (US 20110133242 A1).
Regarding claim 8, Sano/Sung fails to disclose the light emitting diode according claim 1, wherein an upper surface of the first-type semiconductor layer is provided with a roughened structure.
Choi discloses wherein an upper surface of the first-type semiconductor layer (110) is provided with a roughened structure (112, Fig. 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the roughened surface of Choi in Sano/Sung so as to increase light extraction efficiency (Choi, [0057]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (US 20030141506 A1) in view of Sung et al. (US 20190051797 A1) as applied to claim 1 above, and further in view of Ito (US 20200119230 A1).
Regarding claim 18, Sano/Sung fails to disclose the light emitting diode according claim 1, wherein a backside metallization layer is disposed on an outer surface side of the substrate.
Ito discloses wherein a backside metallization layer (10) is disposed on an outer surface side of the substrate (2, Fig. 1, [0085]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the metallization Ito in Sano/Sung so as to facilitate formation of electrode and facilitate electrical driving of an LED since the use of conventional materials to perform their known function is prima-facie obvious (See MPEP 2144.07).
Response to Arguments
Applicant's arguments filed 6.10.2026 have been fully considered but they are not persuasive.
The applicant alleges Fig. 3E of Sano et al. (US 20030141506 A1) fails to disclose or or suggest “the current-blocking layer is located between the adhesion layer and the second-type semiconductor layer, and the adhesion layer is a transparent oxide layer”. The examiner agrees with the applicant but notes that the instant rejection relies on Fig. 12F such that Sano discloses the current-blocking layer (4b) is located between the adhesion layer (4a) and the second-type semiconductor layer (2a), and the adhesion layer (4a) is a transparent oxide layer ([0029] SiO2).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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