Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 10, 11, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Klowak (US 20160240471 A1).
Regarding claim 1, Klowak discloses, in figures 2A, 2B, and 2C, a “semiconductor device structure” which may be used for high power transistors (abstract, describes transistor package). The package has a transistor chip 102 with a first side and a second side opposite the first side, ‘source contact’ 112, ‘drain contact’ 114, and ‘gate contact’ 116 (electrode metallizations), see paragraph 0054. Additionally, ‘copper foil layers’ 130 (first structured metal layer) comprise a ‘drain contact area’ 134, ‘source contact area’ 132, and ‘gate contact areas’ 136, and is facing the first side of the of the power transistor chip (electrode metallizations). FIG. 2B shows a second ‘copper foil’ layer 140, which has a ‘source contact pad’ 142, ‘drain contact pad’ 144, ‘gate contact pad’ 146, and ‘source sense contact pad’ 148 (all of which can be called package terminal pads, see FIG. 2B). Further, ‘dielectric body’ 127 is between the two structured metal layers, and the structured metal layers metal layers have a plurality of vias 190 running through the insulating layer 127 connecting portions of the first structured metal layer to the terminal pads of the second structured metal layer. Finally, the source-sense terminal pad is only on the second structured metal layer, so the gate-source current path goes only to the second structured metal layer, while the drain-source current path runs through both layers (as evidenced by the metallizations for the drain and source on both structured metal layers). The combined structure of the two metallization layers and the insulating layer makes up a multi-layered laminate substrate.
Regarding claim 3, as shown above, Klowak discloses that the drain-source current path is on both the first and second structured metal layers, while the gate-source current path is only on the second structured metal layer.
Regarding claim 5, Klowak further discloses, in FIG. 2B, that the source sense package terminal pad and the source package terminal pad are formed by separate metal segments of the second structured metal layer.
Regarding claim 10, Klowak further discloses, in FIG. 4A, a dedicated via (directly on source sense package terminal pad 448) in through which no drain-source current is flowing.
Regarding claim 11, Klowak further discloses, in FIG. 1A, that the first structured metal layer comprises a multi-finger drain segment connected to the drain electrode metallization (see FIG. 2C), and a multi-finger source-electrode metallization connected to the source electrode metallization, wherein both segments are interdigitated.
Regarding claim 15, Klowak further discloses in paragraph 0052, that the power transistor chip 102 comprises a lateral GaN power transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The examiner notes that foreign patent literature is cited in this action. Hereafter, all quotations and figure numbers refer to the foreign patent document as it appears in the translated copy provided with this action.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klowak (US 20160240471 A1) in view of Ueda (US 20210336017 A1).
Regarding claim 2, Klowak discloses the limitations of claim 1, as shown above. However, Klowak does not discloses that the source sense package terminal pad and the source package terminal pad are formed by a continuous metal segment.
Ueda teaches, in FIG. 7, a “source kelvin electrode” MSS, which is formed of the same continuous metal segment as “main MOS source electrode” MSF.
It would have been obvious to one having ordinary skill in the art to modify the transistor package taught by Klowak such that the source sense package terminal pad and the source package terminal pad are formed of a continuous metal segment of the second structured metal layer, as taught by Ueda. One having ordinary skill in the art would be motivated to do so in order to, for example reduce the area of etching after the deposition of the second structured metal layer, thereby reducing the risk of over-etching and increasing yield.
Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klowak (US 20160240471 A1) in view of Suzuki (JP H08340082 A).
Regarding claim 4, Klowak discloses that the drain-source current path is on both the first and second structured metal layers, while the gate-source current path is only on the second structured metal layer, as shown above. Additionally, the structures of the first and second structured metal layers (FIG. 2A and 2B) show lateral conductive paths for the source-drain and gate-source current paths to flow.
Klowak does not disclose that the drain-source and gate-source current paths go in two different lateral directions.
Suzuki teaches, in paragraph 23 of “Description of the Preferred Embodiments,” that the structure described by FIG. 1 has the property that the drain-source current foes not at all flow in the gate-source path.
It would have been obvious to one having ordinary skill in the art to modify the transistor package taught by Klowak such that the drain-source current path is in a lateral direction Y, which is different from a lateral direction X which the gate-source current path flows on the first and second structured metal layers. Suzuki teaches that such a setup reduces power consumption and eliminates the loss effect of switching (paragraph 23 of “Description of the Preferred Embodiments”).
Regarding claim 8, as shown above, Klowak discloses two structured metal layers, wherein the source-drain current flows on the first and second structured metal layers, and the gate-source current flows on the second structured metal layer.
Also shown above, Suzuki teaches the complete decoupling of the source-drain and gate-source current paths.
It would have been obvious to one of ordinary skill in art to modify the transistor packaging structure taught by Klowak such that the drain-source current path is only on the second structured metal layer and that the gate-source current path is only on the first metal layer. One having ordinary skill in the art is motivated to do so by the benefits taught by Suzuki above. The examiner notes that, with only two metal layers, there are only two possibilities for routing the source-gate and gate-source currents such that they are on different layers (and thus ensuring that their current paths are decoupled).
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klowak (US 20160240471 A1.
Regarding claim 6, As shown above, Klowak discloses that the drain-source current path is on the first and second structured metal layers, and that the gate-source current path is on the second structured metal layer. Klowak does not disclose that the gate-source current path is on the first structured metal layer
It would have been obvious to one of ordinary skill in the art to simply exchange the structured metal layer in which the gate-source current path flows in the overall transistor packaging structure taught by Klowak. The examiner notes that, in this context, the elements of the ‘first structured metal layer’ taught by Klowak could be used as package terminal pads, and thus the first structured metal lay could become the second structured metal layer and vice-versa, as is appreciated by one having ordinary skill in the art. One having ordinary skill in the art would be motivated to do so in order to, for example, reduce parasitic inductance in the packaging structure by ensuring the partial separation of the gate-source and source-drain current paths, reducing parasitic inductance.
Regarding claim 16, Klowak teaches, in paragraph 0005, a GaN power device patent included as a reference for which “a breakdown voltage exceeding 1200V can be achieved.” Later, in paragraph 0007, Klowak teaches that improved interconnect and packaging schemes are required to take advantage of such a structure (and that the rest of the disclosure will do so). This therefore teaches that the aforementioned patent, included as a reference to Klowak, in combination with the aforementioned structure of claim 1, teaches a transistor chip configured to switch drain-source voltages greater than 50 V.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klowak (US 20160240471 A1) in view of Roberts (US 20160380090 A1) .
Regarding claim 12, Klowak teaches the limitations of claim 1, and that the source package terminal is arranged along a fist side of the package, and the drain terminal is arranged along a second side.
Klowak does not teach that the gate package terminal is arranged at a corner of the first side of the package.
Roberts teaches, in FIG. 7A, a semiconductor package with a source terminal pad 762 on a first side and a drain terminal pad 764, on a second side, with a gate package terminal pad, 766, arranged at a corner of the first side of the transistor package.
It would have been obvious to one having ordinary skill in the art to modify Klowak with Roberts such that the package terminal pads are in the above described orientation. One having ordinary skill in the art is motivated to create such a terminal pad layout in order to, for example, ensure that the gate and drain terminal pads are spaced apart, decreasing parasitic inductance.
Regarding claim 13, Roberts further teaches that the source package terminal pad is arranged along a first side of the transistor package, and that the drain package terminal pad is arranged along a second side opposite the first, as shown above, and further teaches, in FIG. 7A, a gate package terminal pad arrange at a third side of the transistor package in a region spaced apart from a corner of the first or second side of the transistor package.
It would have been obvious to one having ordinary skill in the art to modify the transistor packaging structure taught by Klowak such that the source package terminal pad is arranged along a first side of the transistor package and the drain package terminal pad is arranged along a second side of the transistor package, and the gate package terminal pad is arranged along a third side which is spaced apart from a corner of the first or second side of the transistor package, as taught by Roberts. One having ordinary skill in the art would be motivated to do so in order to ensure that the gate and drain terminal pads are spaced apart, decreasing parasitic inductance.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klowak (US 20160240471 A1) in view of McKnight (US 9589868 B2).
Regarding claim 14, Klowak teaches the limitations of claim 1, however, Klowak does not teach a mold compound covering the substrate outside of the transistor chip.
McKnight teaches, in FIG 4 (prior art), a “GaN-on-Si” die which is surrounded by a “module fill” (mold compound embedding) 209. The examiner notes that the mold compound embedding is on the “cool plate metallization” 203, and “cool plate ceramic” 201 (multilayer laminate substrate).
It would have been obvious to one having ordinary skill in the art to include the mold compound embedding taught by McKnight in the overall transistor package taught by Klowak. One having ordinary skill in the art is motivated to do so in order to, for example, further protect the power chip from oxidation.
Conclusion
References cited, not used:
“Gate Drives and Gate Driving with SiC MOSFETs” (Wolfspeed) – teaches the importance of keeping gate-driving circuit and power circuit completely separated (in section “Some PCB layout tips and tricks”).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897