DETAILED ACTION
This Action is responsive to the communication filed on 10/17/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen (US 2023/0260977).
Regarding claim 1, Chen (see, e.g., FIG. 11 (inverted)) discloses a semiconductor apparatus comprising:
a semiconductor layer 124, 126, 128 comprising a first surface e.g., bottom surface and a second surface e.g., top surface that is opposite to the first surface e.g., bottom surface (Para 0037);
a first wire structure 130B on the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128 (Para 0036, Para 0038);
a second wire structure 130A on the second surface e.g., top surface of the semiconductor layer 124, 126, 128 (Para 0036, Para 0038); and
a through via 136 that extends through the semiconductor layer 124, 126, 128 and is electrically connected to the first wire structure 130B and the second wire structure 130A,
wherein:
the semiconductor layer 124, 126, 128 comprises a first semiconductor element layer 128 that is adjacent to the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128 (Para 0036), and
wherein the semiconductor layer 124, 126, 128 comprises a second semiconductor element layer 126 that is adjacent to the second surface e.g., top surface of the semiconductor layer 124, 126, 128 (Para 0036).
Regarding claim 2, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 1, further comprising: a logic die 102A on a surface of the first wire structure 130B that is opposite to the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128 (Para 0032).
Regarding claim 3, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 2, further comprising: a carrier substrate 1024 on a surface of the second wire structure 130A that is opposite to the second surface e.g., top surface of the semiconductor layer 124, 126, 128 (Para 0053).
Regarding claim 4, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 2, wherein: the first wire structure 130B includes a conductive pad 134A (see also FIG. 1A) on the surface of the first wire structure 130B (Para 0038).
Regarding claim 14, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 1, further comprising: a carrier substrate 1024 on a surface of the second wire structure 130A that is opposite to the second surface e.g., top surface of the semiconductor layer 124, 126, 128 (Para 0053).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2023/0260977), in view of Jeong (US 2022/0077078).
Regarding claim 5, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 2, wherein: the first wire structure 130B and the second wire structure 130A each comprises a plurality of metal line layers e.g., horizontal metal lines, a plurality of connection vias e.g., vertical metal vias that electrically connect the plurality of metal line layers e.g., horizontal metal lines to each other, and interlayer insulating layer 142 that electrically isolate the plurality of metal line layers e.g., horizontal metal lines from each other (Para 0038, Para 0042),
Although Chen shows substantial features of the claimed invention, Chen fails to expressly teach a plurality of interlayer insulating layers.
Jeong (see, e.g., FIG. 1B, FIG. 2B) teaches a wire structure 110 having a plurality of interlayer insulating layers 111 for the purpose of improving the reliability of the package by minimizing an increase in manufacturing costs, and preventing the occurrence of cracks in the outermost insulating layer (Para 0034, Para 0035).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wire structures of Chen to include a plurality of interlayer insulating layers as described by Jeong for the purpose of improving the reliability of the package by minimizing an increase in manufacturing costs, and preventing the occurrence of cracks in the outermost insulating layer (Para 0035).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2023/0260977), in view of Yeh (US 2022/0230969).
Regarding claim 6, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 2, further comprising: a plurality of bumps 120A on a surface of the logic die 102A that is opposite to the surface of the first wire structure 130B (Para 0031).
Although Chen shows substantial features of the claimed invention, Chen fails to expressly teach a plurality of micro bumps. However, Chen does teach that the bonding structures 120A include solder bumps (Para 0031)
Yeh (see, e.g., FIG. 3A), on the other hand, teaches that the electrical connections 110 includes either micro-bumps or solder bumps (Para 0019).
Therefore, it would have been obvious at the time of filing the invention to one or ordinary skill in the art to use either micro-bumps or solder bumps in Chen’s device because these were recognized in the semiconductor art for their use as electrical connectors, as taught by Yeh, and selecting between known equivalents would be within the level of ordinary skill in the art.
Regarding claim 7, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 6, further comprising: a carrier substrate 1024 on a surface of the second wire structure 130A that is opposite to the second surface of the semiconductor layer 124, 126, 128 (Para 0053).
Regarding claim 8, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 1, further comprising: a plurality of bumps 112A on a surface of the first wire structure 130B that is opposite to the surface of the semiconductor layer 124, 126, 128 (Para 0029).
Although Chen shows substantial features of the claimed invention, Chen fails to expressly teach a plurality of micro bumps. However, Chen does teach that the conductive bonding structures 112A include solder bumps, copper bumps, copper pillars, or any other suitable conductive bonding structures (Para 0031)
Yeh (see, e.g., FIG. 3A), on the other hand, teaches that the electrical connections 110 includes either micro-bumps or solder bumps (Para 0019).
Therefore, it would have been obvious at the time of filing the invention to one or ordinary skill in the art to use either micro-bumps or solder bumps in Chen’s device because these were recognized in the semiconductor art for their use as electrical connectors, as taught by Yeh, and selecting between known equivalents would be within the level of ordinary skill in the art.
Regarding claim 9, Chen (see, e.g., FIG. 11 (inverted)) teaches the semiconductor apparatus of claim 8, further comprising: a carrier substrate 1024 on a surface of the second wire structure 130A that is opposite to the second surface e.g., top surface of the semiconductor layer 124, 126, 128 (Para 0053).
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2023/0260977), in view of Yeh (US 2022/0230969), and further in view of Kim (US 2022/0077066).
Regarding claim 10, although Chen/Yeh shows substantial features of the claimed invention, Chen/Yeh fails to expressly teach the semiconductor apparatus of claim 9, further comprising: a mounting substrate on the plurality of micro bumps.
Kim (see, e.g., FIG. 11) teaches a mounting substrate 800 on the plurality of bumps 400 for the purpose of transmitting external electrical signals to the semiconductor chips of the package (Para 0022, Para 0063-Para 0065).
The combination of Chen (see, e.g., FIG. 11 (inverted)) / Yeh (see, e.g., FIG. 3A) / Kim (see, e.g., FIG. 11) teaches a mounting substrate 800 (as taught by Kim) on the plurality of micro bumps 120A (as taught by Chen, modified by Yeh).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the mounting substrate as described by Kim to the device of Chen/Yeh for the purpose of transmitting external electrical signals to the semiconductor chips of the package (Para 0064).
Regarding claim 11, Kim (see, e.g., FIG. 11) teaches the semiconductor apparatus of claim 10, wherein: the mounting substrate 800 is a circuit board or an interposer (Para 0064).
Regarding claim 12, although Chen/Yeh shows substantial features of the claimed invention, Chen/Yeh fails to expressly teach the semiconductor apparatus of claim 8, further comprising: a mounting substrate on the plurality of micro bumps.
Kim (see, e.g., FIG. 11) teaches a mounting substrate 800 on the plurality of bumps 400 for the purpose of transmitting external electrical signals to the semiconductor chips of the package (Para 0022, Para 0063-Para 0065).
The combination of Chen (see, e.g., FIG. 11 (inverted)) / Yeh (see, e.g., FIG. 3A) / Kim (see, e.g., FIG. 11) teaches a mounting substrate 800 (as taught by Kim) on the plurality of micro bumps 120A (as taught by Chen, modified by Yeh).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the mounting substrate as described by Kim to the device of Chen/Yeh for the purpose of transmitting external electrical signals to the semiconductor chips of the package (Para 0064).
Regarding claim 13, Kim (see, e.g., FIG. 11) teaches the semiconductor apparatus of claim 12, wherein: the mounting substrate 800 is a circuit board or an interposer (Para 0064).
Allowable Subject Matter
Claims 17-20 are allowed.
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Remarks
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding claim 1, Chen (see, e.g., FIG. 11 (inverted)) discloses a semiconductor apparatus comprising: a semiconductor layer 124, 126, 128 comprising a first surface e.g., bottom surface and a second surface e.g., top surface that is opposite to the first surface e.g., bottom surface (Para 0037); a first wire structure 130B on the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128, wherein the first wire structure 130B comprises a plurality of first metal line layers e.g., horizontal metal lines, a plurality of first connection vias e.g., vertical metal vias that electrically connect the plurality of first metal line layers e.g., horizontal metal lines to each other, and a first interlayer insulating layer 142 that electrically isolate the plurality of first metal line layers e.g., horizontal metal lines from each other (Para 0036, Para 0038, Para 0042); a second wire structure 130A on the second surface e.g., top surface of the semiconductor layer 124, 126, 128, wherein the second wire structure 130A comprises a plurality of second metal line layers e.g., horizontal metal lines, a plurality of second connection vias e.g., vertical metal vias that electrically connect the plurality of second metal line layers e.g., horizontal metal lines to each other, and a second interlayer insulating layer 142 that electrically isolate the plurality of second metal line layers e.g., horizontal metal lines from each other (Para 0036, Para 0038, Para 0042); and a through via 136 that extends through the semiconductor layer 124, 126, 128 and that is electrically connected to the first wire structure 130B and the second wire structure 130A, wherein the semiconductor layer 124, 126, 128 comprises a first semiconductor element layer 128 that is adjacent to the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128, and wherein the semiconductor layer 124, 126, 128 comprises a second semiconductor element layer 126 that is adjacent to the second surface e.g., top surface of the semiconductor layer 124, 126, 128, (Para 0036).
Regarding claim 20, Chen (see, e.g., FIG. 1A (inverted), FIG. 11) discloses a semiconductor apparatus comprising: a semiconductor layer 124, 126, 128 comprising a first surface e.g., bottom surface and a second surface e.g., top surface that is opposite to the first surface e.g., bottom surface (Para 0037); a first wire structure 130B on the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128, wherein the first wire structure 130B comprises a plurality of first metal line layers e.g., horizontal metal lines, a plurality of first connection vias e.g., vertical metal vias that electrically connect the plurality of first metal line layers e.g., horizontal metal lines to each other, and a first interlayer insulating layer 142 that electrically isolate the plurality of first metal line layers e.g., horizontal metal lines from each other (Para 0036, Para 0038, Para 0042); a second wire structure 130A on the second surface e.g., top surface of the semiconductor layer 124, 126, 128, wherein the second wire structure 130A comprises a plurality of second metal line layers e.g., horizontal metal lines, a plurality of second connection vias e.g., vertical metal vias that electrically connect the plurality of second metal line layers e.g., horizontal metal lines to each other, and a second interlayer insulating layer 142 that electrically isolate the plurality of second metal line layers e.g., horizontal metal lines from each other (Para 0036, Para 0038, Para 0042); and a through via 136 that extends through the semiconductor layer 124, 126, 128 and that is electrically connected to the first wire structure 130B and the second wire structure 130A (Para 0036); a logic die 102A bonded to a surface of the first wire structure 130B that is opposite to the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128 (Para 0032); wherein the semiconductor layer 124, 126, 128 comprises a first semiconductor element layer 128 that is adjacent to the first surface e.g., bottom surface of the semiconductor layer 124, 126, 128, and wherein the semiconductor layer 124, 126, 128 comprises a second semiconductor element layer 126 that is adjacent to the second surface e.g., top surface of the semiconductor layer 124, 126, 128, (Para 0036).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights