Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0029420, filed on 3/6/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Note that Translations of foreign patent documents are relied upon in this action. Hereafter, all quotations and figure numbers of foreign patent literature refer to the translation as it appears in the copy thereof attached to this action.
Claim(s) 1-6, 11, and 13-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (CN 103367283 B).
Regarding claim 1, Jung discloses, in FIG. 1A, semiconductor device comprising two active patterns (AR) extending along a first direction, arranged in a second direction intersecting the first direction, each including a central part and two edge parts, with the edge parts being spaced across the central part, with a storage node pad (25a) on a first edge part and a bit line contact (DC) on the central part, FIG. 1B further shows that top surface of the bit line node contact (DC) is higher than a top surface of the storage node pad (25A).
Regarding claim 2, Jung further discloses, in FIG. 1B, that a bottom surface of the bit-line node pad DC is at a same level or higher than a bottom surface of the bit-line node contact DC.
Regarding claim 3, Jung further discloses, in paragraph 16 of Specific implementation Examples, “bit line node contact DC may include, for example, metal silicide, doped polysilicon, metal nitride, metal, and combinations thereof.”
Regarding 4, Jung further discloses a combination of polysilicon and metallic material, as shown above.
Regarding claim 5, Jung further discloses that “bit line node contact DC may include, for example, metal silicide . . . “ (paragraph 16 of Specific Implementation Examples).
Regarding claim 6, Jung further discloses “second spacer 47a” (Specific Implementation Examples paragraph 17) that covers a lateral surface of the bit-line node contact. The examiner notes that this “second spacer” is equivalent to a bit-line node spacer.
Regarding claim 11, Jung further discloses, in FIG. 1A and FIG. 1B, a first and second storage node pad, with the second storage node pad on the first edge part of the second active pattern (see storage node pads 25a in FIG 1A and FIG. 1B, line B-B’), and a “device isolation layer 3 may be provided . . . so as to define at least one active region AR” (paragraph 9 of Specific Implementation Examples). The examiner notes that, in order to “define “ these regions, the device isolation layer must surround them. Additionally, “the isolation pattern 21a may be provided between the adjacent storage node pad[s] 25a” (Specific Implementation Examples, paragraph 10). Here, this “isolation pattern 21a” is equivalent to a pad dielectric pattern, as it achieves the same purpose by the same means, as is known to one having ordinary skill in the art.
Regarding claim 13, Jung discloses, in FIG. 1A, semiconductor device comprising two active patterns (AR) extending along a first direction, arranged in a second direction intersecting the first direction, each including a central part and two edge parts, with the edge parts being spaced across the central part, with a storage node pad (25a) on a first edge part and a bit line contact (DC) on the central part, FIG. 1B further shows a storage node pad 25a on the first edge part of the first active pattern and a “bottom electrode pad BEP” (paragraph 20 of Specific Implementation Examples) on the storage node pad and vertically overlapping a portion of the storage node pad. The examiner nodes that the “bottom electrode pad” is equivalent to a storage node contact, as it is contacting the capacitor CP, which is a data storage means, as seen in FIG. 1B. Finally, FIG. 1B shows that a bottom surface of the storage node contact is at a lower level than a top surface of the bit-line node contact.
Regarding claim 14, Jung further shows, in FIG. 1B, that a top surface of the bit-line node contact is at a higher level than a top surface of the storage node pad.
Regarding claim 15, Jung discloses that the bit-line node contact includes a metallic material, as shown above.
Regarding claim 16, Jung discloses a bit-line node spacer covering a lateral surface of the bit-line node contact, as shown above.
Regarding claim 17, Jung teaches the limitations of claim 13 as shown above. However, Jung does not teach that the storage node pad includes a lower pad and an upper pad, each containing different materials.
Regarding claim 18, Jung further discloses “in plan view, a storage node pad 25a can be rectangular in shape” (Specific Implementation Examples paragraph 11).
Regarding claim 19, Jung discloses, in FIG. 1A, a first and second active pattern ACT extending along a firs direction and arranged along a second direction intersecting the first direction, both the first and second active patterns including a central part, a first edge part, and a second edge part, with the first and second edge parts being spaced from each other across the central part. In addition, a pair of word lines WL can be seen running across the first and second active patterns along the second direction. FIG. 1B shows a storage node pad 25a and a storage node contact BC vertically overlapping a portion of the storage node pad. In addition, FIG 1A shows a first bit line extending along a third direction (intersecting the first and second directions) and on the central part of the first action pattern. FIG. 1B shows a bit-line node contact DC between the first bit line and the central part of the first active pattern, a “bottom electrode pad BEP” (paragraph 20 of Specific Implementation Examples) on the storage node contact. The examiner nodes that the “bottom electrode pad” is equivalent to a storage node contact, as it is contacting the capacitor CP, which is a data storage pattern, as is known by one having ordinary skill in the art. In addition, FIG. 1B shows that a top surface of the bit-line node contact is at a higher level than a top surface of the storage node pad.
Regarding claim 20, Jung further discloses, in FIG. 1A, a third active pattern being co-linear with the first active pattern in the first direction and the third active pattern and the second active pattern being arranged in the third direction, and a second bit line extending along the third direction on the central part of the second active pattern and a central part of the third active pattern.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (CN 103367283 B) in view of Ryu (US 20220045063 A1).
Regarding claim 7, Ryu teaches, in FIG. 28B, a bit line contact DC, in which the bit line node contact has a “bit line . . . sub-spacer 325” (paragraph 0075) covering a lateral surface of the upper the bit line node contact, and a “bit line ohmic pattern 331” right above it (paragraph 0073). The examiner notes that one having ordinary skill in the art can appreciate that the bit line ohmic pattern may be considered to be the upper part of the bit line node contact, and that the ohmic pattern comprises different materials than the lower DC layer due to its resistive properties. In addition, the bit line sub-spacer covers a lateral surface of the upper contact and extends to a lateral surface of the lower contact.
It would have been obvious to one having ordinary skill in the art to combine Jung with Ryo such that the bit-line contact, which is part of the overall semiconductor structure taught by Jung, comprises an upper and lower part comprising different materials, with a bit-line spacer as described above. One having ordinary skill in the art would be motivated to make such a substitution because, for example, this allows for greater electrical resistance, decreasing current draw, and greater insulation of the bit-line node contact with the rest of the device.
Regarding claim 8, Ryo further teaches sub-spacer 321 which is adjacent to (and therefore covering, even though it is not in direct contact with) a lateral surface of the bit-line node spacer.
Regarding claim 9, Ryo further teaches a lower contact and upper contact of the bit-line node contact including different materials, as shown above. Additionally, FIG. 28B teaches a gapfill layer 321 which will be appreciated by one having ordinary skill in the art to function as a buffer layer. Additionally, the trench buried pattern is between the buffer pattern and the lower contact.
Regarding claim 10 Jung further teaches, in FIG. 1B, that the bit-line node contact (shown above) has a width at the bottom that, in a third direction intersecting the first and second directions, has a with at the bottom surface that is greater than a width at a top surface; Jung teaches that because of this, “. . . it is possible to reduce the storage node pad 25a and the first doped region 11[‘s] . . . contact resistance” (paragraph 11 of Specific Implementation Examples).
However, Jung does not teach that the bit-line node contact includes a lower contact and an upper contact.
Ryu teaches a bit-line node contact with a lower contact and an upper contact which include different materials, as shown above.
It would have been obvious to one having ordinary skill in the art to combine Jung with Ryu such that the bit-line node contact which is wider at the top than at the bottom, and comprises two layers as taught by Ryo. One having ordinary skill in the art is motivated to make such a substitution for the reasons shown above.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (CN 103367283 B) in view of Jang (US 20230045674 A1).
Jung teaches, in FIG. 1A, a second storage node pad located on the first edge part of the second active pattern, and a device isolation pattern, as shown above.
However, Jung does not teach that the device isolation layer is disposed between the two storage node pads.
Jang teaches, in FIG. 2 and FIG. 3, two storage node pads (CP) which are separated across two active regions by a “first device isolation layer 101a” (paragraph 0021).
It would have been obvious to one having ordinary skill in the art to modify Jung with Jang such that the semiconductor structure described by Jung has storage node pads that are separated by a device isolation layer as taught by Jang. One having ordinary skill in the art is motivated to isolate the storage node pads with the device isolation layer in order to, for example, ensure the electrical isolation of different storage nodes without having to manufacture an additional layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday - Friday, 8:30 a.m. - 5 p.m. ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897