DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election without traverse of Invention I (i.e., claims 1-19) in the reply filed on June 16th, 2026 is acknowledged. Claims 20-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention.
Claim Rejections - 35 USC § 112
Claims 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 at line 8 requires “the first surface of the first stage of the multi-stage via being proximate the second side of the semiconductor structure.” However, lines 6-7 require “the first surface of the first stage of the multi-stage via being proximate the first side of semiconductor structure.” Is the first surface of the first stage proximate the second side or the first side of the semiconductor structure? For the purposes of examination, the limitation ““the first surface of the first stage of the multi-stage via being proximate the second side of the semiconductor structure” at line 8 is understood to be --the first surface of the second stage of the multi-stage via being proximate the second side of the semiconductor structure--. Claims 15 and 16 are also rejected as they depend from claim 17 and do not clear up the uncertainty.
Claim 17 at line 8 requires “the first surface of the first stage of the multi-stage via being proximate the second side of the semiconductor structure.” However, lines 6-7 require “the first surface of the first stage of the multi-stage via being proximate the first side of semiconductor structure.” Is the first surface of the first stage proximate the second side or the first side of the semiconductor structure? For the purposes of examination, the limitation ““the first surface of the first stage of the multi-stage via being proximate the second side of the semiconductor structure” at line 8 is understood to be --the first surface of the second stage of the multi-stage via being proximate the second side of the semiconductor structure--. Claims 18 and 19 are also rejected as they depend from claim 17 and do not clear up the uncertainty.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8-14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawaguchi (US 2022/0052068 A1).
With respect to claim 1, Kawaguchi teaches a semiconductor structure in at least Fig. 22, comprising:
a multi-stage via SLT comprising a first stage (UST at 31U) and a second stage (LST at 31L) (see Fig. 22 and paragraphs 139, 141, 142);
the first stage (UST at 31U) of the multi-stage via having a first surface (UST at uppermost 31U in Fig. 22) and a second surface (bottom of UST in Fig. 22), the first surface of the first stage of the multi-stage via having a first diameter and the second surface of the first stage of the multi-stage via having a second diameter, the second diameter of the second surface of the first stage of the multi-stage via being smaller than or equal to the first diameter of the first surface of the first stage of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142; note UST wider at uppermost 31U than bottom of UST in Fig. 22);
the second stage (LST at 31L) of the multi-stage via having a first surface (LST at widest part in Fig. 22) and a second surface (top of LST in Fig. 22), the first surface of the second stage of the multi-stage via having a first diameter and the second surface of the second stage of the multi-stage via having a second diameter, the second diameter of the second surface of the second stage of the multi-stage via being smaller than or equal to the first diameter of the first surface of the second stage of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142; note LST wider in the middle than at top of LST in Fig. 22);
wherein the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via is proximate a first side (top in Fig. 22) of the semiconductor structure and the first surface of the second stage (LST at 31L) of the multi-stage via is proximate a second side (bottom in Fig. 22) of the semiconductor structure, the second side of the semiconductor structure being opposite the first side of the semiconductor structure (see Fig. 22 and paragraphs 139, 141, 142); and
wherein the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via abuts the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142).
With respect to claim 2, Kawaguchi teaches the semiconductor structure of claim 1, wherein the multi-stage via provides power delivery from a power delivery network at the second side (bottom in Fig. 22) of the semiconductor structure to a portion of a transistor structure (memory cell transistors at 31 and select transistors at 32) proximate the first side (top in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 68, 77).
With respect to claim 3, Kawaguchi teaches the semiconductor structure of claim 2, wherein the portion of the transistor structure proximate the first side (top in Fig. 22) of the semiconductor structure comprises a source/drain region of the transistor structure (see Fig. 22 and paragraphs 45, 77, 89).
With respect to claim 4, Kawaguchi teaches the semiconductor structure of claim 2, wherein the transistor structure comprises a stacked transistor structure comprising a first transistor (one of the memory cell transistors at 31) and a second transistor (another of the memory cell transistors at 31) stacked over the first transistor, and wherein the portion of the transistor structure comprises a source/drain region of the second transistor (see Fig. 22 and paragraphs 45, 77, 89).
With respect to claim 6, Kawaguchi teaches the semiconductor structure of claim 1, wherein the multi-stage via SLT provides a signal connection between the first side (top in Fig. 22) of the semiconductor structure and the second side (bottom in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 77, 89, 141; note LI of SLT used as source line).
With respect to claim 8, Kawaguchi teaches the semiconductor structure of claim 1, wherein the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via SLT abuts the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT proximate a midpoint between the first side (top in Fig. 22) of the semiconductor structure and the second side (bottom in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 139, 141, 142; note midpoint at dashed line between UST and LST).
With respect to claim 9, Kawaguchi teaches the semiconductor structure of claim 1, wherein at least one of: the second diameter of the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via SLT is smaller than the first diameter of the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via SLT; and the second diameter of the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT is smaller than the first diameter of the first surface (LST at widest part in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT (see Fig. 22 and paragraphs 139, 141, 142; note diameter differences in Fig. 22).
With respect to claim 10, Kawaguchi teaches an integrated circuit in at least Fig. 22 comprising:
a semiconductor structure comprising:
a multi-stage via SLT comprising a first stage (UST at 31U) and a second stage (LST at 31L) (see Fig. 22 and paragraphs 139, 141, 142);
the first stage (UST at 31U) of the multi-stage via having a first surface (UST at uppermost 31U in Fig. 22) and a second surface (bottom of UST in Fig. 22), the first surface of the first stage of the multi-stage via having a first diameter and the second surface of the first stage of the multi-stage via having a second diameter, the second diameter of the second surface of the first stage of the multi-stage via being smaller than or equal to the first diameter of the first surface of the first stage of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142; note UST wider at uppermost 31U than bottom of UST in Fig. 22);
the second stage (LST at 31L) of the multi-stage via having a first surface (LST at widest part in Fig. 22) and a second surface (top of LST in Fig. 22), the first surface of the second stage of the multi-stage via having a first diameter and the second surface of the second stage of the multi-stage via having a second diameter, the second diameter of the second surface of the second stage of the multi-stage via being smaller than or equal to the first diameter of the first surface of the second stage of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142; note LST wider in the middle than at top of LST in Fig. 22);
wherein the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via is proximate a first side (top in Fig. 22) of the semiconductor structure and the first surface of the second stage (LST at 31L) of the multi-stage via is proximate a second side (bottom in Fig. 22) of the semiconductor structure, the second side of the semiconductor structure being opposite the first side of the semiconductor structure (see Fig. 22 and paragraphs 139, 141, 142); and
wherein the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via abuts the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142).
With respect to claim 11, Kawaguchi teaches the integrated circuit of claim 10, wherein the multi-stage via provides power delivery from a power delivery network at the second side (bottom in Fig. 22) of the semiconductor structure to a portion of a transistor structure (memory cell transistors at 31 and select transistors at 32) proximate the first side (top in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 68, 77).
With respect to claim 12, Kawaguchi teaches the integrated circuit of claim 10, wherein the multi-stage via SLT provides a signal connection between the first side (top in Fig. 22) of the semiconductor structure and the second side (bottom in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 77, 89, 141; note LI of SLT used as source line).
With respect to claim 13, Kawaguchi teaches the integrated circuit of claim 10, wherein the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via SLT abuts the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT proximate a midpoint between the first side (top in Fig. 22) of the semiconductor structure and the second side (bottom in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 139, 141, 142; note midpoint at dashed line between UST and LST).
With respect to claim 14, Kawaguchi teaches a semiconductor structure in at least Fig. 22, comprising:
a stacked transistor structure comprising a first transistor (one of the memory cell transistors at 31U) vertically stacked over a second transistor (another of the memory cell transistors at 31L), the first transistor being proximate a first side (top in Fig. 22) of the semiconductor structure and the second transistor being proximate a second side (bottom in Fig. 22) of the semiconductor structure opposite the first side of the semiconductor structure (see Fig. 22 and paragraphs 45, 77, 89, 139, 141, 142);
a multi-stage via SLT comprising a first stage (UST at 31U) and a second stage (LST at 31L), each of the first stage and the second stage having a first surface and a second surface opposite the first surface, the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via being proximate the first side (top in Fig. 22) of the semiconductor structure, the first surface (LST at widest part in Fig. 22) of the second stage (LST at 31L) of the multi-stage via being proximate the second side (bottom in Fig. 22) of the semiconductor structure, and the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via abutting the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT (see Fig. 22 and paragraphs 139, 141, 142; note in Fig. 22 that UST wider at uppermost 31U, and LST wider in the middle than at top of LST);
wherein the multi-stage via SLT connects a power delivery network proximate the second side (bottom in Fig. 22) of the semiconductor structure to a source/drain region of the first transistor (one of the memory cell transistors at 31U) (see Fig. 22 and paragraphs 45, 68, 77, 89; note LI of SLT used as source line);
wherein a first diameter of the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via is greater than or equal to a second diameter of the second surface of the second stage (top of LST in Fig. 22) of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142; note UST wider at uppermost 31U than to of LST); and
wherein a first diameter of the first surface (LST at widest part in Fig. 22) of the second stage (LST at 31L) of the multi-stage via is greater than or equal to a second diameter of the second surface (top of LST in Fig. 22) of the second stage of the multi-stage via (see Fig. 22 and paragraph 139, 141, 142; note LST wider in the middle than at top of LST in Fig. 22).
With respect to claim 16, Kawaguchi teaches the semiconductor structure of claim 14, wherein the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via SLT abuts the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT proximate a midpoint between the first side (top in Fig. 22) of the semiconductor structure and the second side (bottom in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 139, 141, 142; note midpoint at dashed line between UST and LST).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi (US 2022/0052068 A1) in view of Cheng et al. (US 11,158,544 B2; hereinafter Cheng).
With respect to claim 5, Kawaguchi discloses the semiconductor structure of claim 4.
Kawaguchi does not explicitly disclose wherein the first transistor and the second transistor comprise respective nanosheet transistors.
Cheng discloses a semiconductor structure in at least Figs. 10-10B in wherein a first transistor and a second transistor comprise respective nanosheet transistors (see Figs. 10-10B, column 4, line 57 - column 5, line 11, and column 5, line 45-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first transistor and the second transistor of Kawaguchi would comprise respective nanosheet transistors as taught by Cheng because for forming vertically stacked nanosheet transistors improves transistor density in unit chip area and improves the device isolation (see Cheng: column 5, line 4-7).
With respect to claim 15, Kawaguchi discloses the semiconductor structure of claim 14.
Kawaguchi does not explicitly disclose wherein the first transistor and the second transistor comprise respective nanosheet transistors.
Cheng discloses a semiconductor structure in at least Figs. 10-10B in wherein a first transistor and a second transistor comprise respective nanosheet transistors (see Figs. 10-10B, column 4, line 57 - column 5, line 11, and column 5, line 45-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first transistor and the second transistor of Kawaguchi would comprise respective nanosheet transistors as taught by Cheng because for forming vertically stacked nanosheet transistors improves transistor density in unit chip area and improves the device isolation (see Cheng: column 5, line 4-7).
Claims 7 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi (US 2022/0052068 A1) in view of Li et al. (US 2022/0020665 A1; hereinafter Li).
With respect to claim 7, Kawaguchi discloses the semiconductor structure of claim 6.
Kawaguchi does not explicitly disclose wherein the signal connection is between a first back-end-of-line structure disposed on the first side of the semiconductor structure and a second back-end-of-line structure disposed on the second side of the semiconductor structure.
Li discloses a semiconductor structure in Figs. 1-4 wherein a signal connection (source connections) is between a first back-end-of-line structure disposed on a first side of the semiconductor structure and a second back-end-of-line structure disposed on the second side of the semiconductor structure (see Fig. 1-4 and paragraphs 28, 49, 52, 54, 60, 62, 64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the signal connection of Kawaguchi would be between a first back-end-of-line structure disposed on the first side of the semiconductor structure and a second back-end-of-line structure disposed on the second side of the semiconductor structure as taught by Li. By performing a frontside and a backside BEOL metallization process, the IC may implement techniques for multi-dimensional (e.g., 3D) vertical chip integration that reduces PDN IR drop and may be compatible with other desired manufacturing processes (e.g., such as a complementary-metal-oxide-semiconductor (CMOS) process) while avoiding high manufacturing costs (see Li: paragraph 4).
With respect to claim 17, Kawaguchi discloses a semiconductor structure in at least Fig. 22, comprising:
a first structure (comprising V0, 35) proximate a first side (top in Fig. 22) of the semiconductor structure (see Fig. 22 and paragraphs 94, 95, 138);
a second structure (comprising 20, 21) proximate a second side (bottom in Fig. 22) of the semiconductor structure opposite the first side of the semiconductor structure (see Fig. 22 and paragraphs 62, 63, 138, 140); and
a multi-stage via SLT comprising a first stage (UST at 31U) and a second stage (LST at 31L), each of the first stage and the second stage having a first surface and a second surface opposite the first surface, the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via being proximate the first side (top in Fig. 22) of the semiconductor structure, the first surface (LST at widest part in Fig. 22) of the second stage (LST at 31L) of the multi-stage via being proximate the second side (bottom in Fig. 22) of the semiconductor structure, and the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via abutting the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT (see Fig. 22 and paragraphs 139, 141, 142; note in Fig. 22 that UST wider at uppermost 31U, and LST wider in the middle than at top of LST);
wherein the multi-stage via SLT provides a signal connection between the first structure and the second structure (see Fig. 22 and paragraphs 77, 89, 95, 141; note LI of SLT used as source line);
wherein a first diameter of the first surface (UST at uppermost 31U in Fig. 22) of the first stage (UST at 31U) of the multi-stage via is greater than or equal to a second diameter of the second surface of the second stage (top of LST in Fig. 22) of the multi-stage via (see Fig. 22 and paragraphs 139, 141, 142; note UST wider at uppermost 31U than to of LST); and
wherein a first diameter of the first surface (LST at widest part in Fig. 22) of the second stage (LST at 31L) of the multi-stage via is greater than or equal to a second diameter of the second surface (top of LST in Fig. 22) of the second stage of the multi-stage via (see Fig. 22 and paragraph 139, 141, 142; note LST wider in the middle than at top of LST in Fig. 22).
Kawaguchi does not explicitly disclose a first back-end-of-line structure and a second back-end-of-line structure.
Li discloses a semiconductor structure in Figs. 1-4 wherein a signal connection (source connections) is between a first back-end-of-line structure disposed on a first side of the semiconductor structure and a second back-end-of-line structure disposed on the second side of the semiconductor structure (see Fig. 1-4 and paragraphs 28, 49, 52, 54, 60, 62, 64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor structure of Kawaguchi would include a first back-end-of-line structure and a second back-end-of-line structure as taught by Li. By performing a frontside and a backside BEOL metallization process, the IC may implement techniques for multi-dimensional (e.g., 3D) vertical chip integration that reduces PDN IR drop and may be compatible with other desired manufacturing processes (e.g., such as a complementary-metal-oxide-semiconductor (CMOS) process) while avoiding high manufacturing costs (see Li: paragraph 4).
With respect to claim 18, the combination of Kawaguchi and Li discloses the semiconductor structure of claim 17, wherein the multi-stage via provides the signal connection (source connections) between a first metallization layer of the first back-end-of-line structure and a second metallization layer of the second back-end-of-line structure (see Li: Fig. 1-4 and paragraphs 28, 49, 52, 54, 60, 62, 64).
With respect to claim 19, Kawaguchi teaches the semiconductor structure of claim 17, wherein the second surface (bottom of UST in Fig. 22) of the first stage (UST at 31U) of the multi-stage via SLT abuts the second surface (top of LST in Fig. 22) of the second stage (LST at 31L) of the multi-stage via SLT proximate a midpoint between the first side (top in Fig. 22) of the semiconductor structure and the second side (bottom in Fig. 22) of the semiconductor structure (see Kawaguchi: Fig. 22 and paragraphs 139, 141, 142; note midpoint at dashed line between UST and LST).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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