Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/30/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yun (US 20210143172 A1).
Regarding claim 1, Yun discloses, in FIG. 2A, a semiconductor device comprising “stacked” structure 6, which comprises “insulating layers” 9 and “gate layers” 12 in which “The gate layers 12 may include a conductive material” (paragraph 0062), meaning that the stacked structure is a gate stacked structure. FIG. 2A further shoes “vertical memory structure” 18a which comprises a hole extending in a vertical direction into the gate stacked structure. FIG. 3A shows a plan view of the device (paragraph 0017) in which Yun further discloses that the vertical memory structure comprises a first sidewall and a second sidewall (at the boundary of the vertical memory structure with the gate stacked structure in the top (+y) and bottom (-y) portions of FIG. 3A) facing each other, “a pair of separation structures” (first and second separation patterns) 35a facing each other and that contact a boundary portion between the first sidewall and the second sidewall and in which first and second separation patterns facing each other and extending in the vertical direction (“separation structures 35 may be disposed to penetrate through the stacked structure,” paragraph 0064); FIG. 3A further shows a “first data storage structure” (first plug pattern) 20a_1 contacting the first sidewall and extending in a vertical direction (see FIG. 2A) and a “second data storage structure” (second plug pattern) 20b_1 contacting the second sidewall and extending in the vertical direction (see FIG. 2A).
Regarding claim 2, Yun further discloses, in FIG. 3A, that the first plug pattern 20a_1 and the second plug pattern respectively comprise a “first dielectric layer” (first and second blocking insulating layers, which contact the first and second sidewalls) 21, a “data storage layer” 23 (“The data storage layer[s] 23 may be a charge trap layer capable of trapping charge,” paragraph 0074, also note that the charge trap layers contact inner walls of the first and second blocking insulating layers), a “second dielectric layer” (tunnel insulating layers, which contact inner walls of the first and second charge trap layers) 25, and first and second “channel semiconductor layer[s]” 27a_1 and 27b_1 which contact an inner wall of the first and second tunnel insulating layers. The examiner notes that the “second dielectric layer” is by definition a tunnel insulating layer as it stands between a channel layer and a charge trap layer.
Regarding claim 3, Yun further teaches, in FIG. 3A, that the first and second blocking insulating layers are coupled to each other along sidewalls of the first and second separation patterns. The examiner notes that another equivalent statement is to say that the first and second separation patterns are connected to each other via following a path outlined by the sidewalls of the first and second separation patterns.
Regarding claim 4, Yun further discloses, in FIG. 3A, that the first and second charge trap layers are spaced apart from each other by the first and second separation patterns.
Regarding claim 5, Yun further discloses, in FIG. 3A, that the first and second channel layers are space apart from each other by the first and second separation patterns.
Regarding claim 6, Yun further discloses, in FIG. 3A, that the first and second plug patterns have symmetrical structures with respect the “X” direction (first horizontal direction) which is orthogonal to the “Z” direction (vertical direction).
Regarding claim 7, Yun further discloses, in FIG. 3A, that the first and second separation patterns have symmetrical structures with respect to the “Y” (second horizontal direction), which is orthogonal to the “Z” (vertical direction) and “X” (first horizontal direction) directions.
Regarding claim 8, Yun further teaches, in FIG. 3A, that the first and second separation patterns each include a first curved surface (see annotated FIG. 3A below) that is convex in relation to outside the hole and a second curved surface that is concave (see annotated FIG. 3A below) in relation to a center of the hole.
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Regarding claim 9, Yun further teaches, in FIG. 3A, that the first and second separation patterns include a first curved surface that is convex in relation to outside of the hole (see annotated FIG. 3A below) and a second curved surface that is convex in relation to a center of the hole (see annotated FIG. 3A below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun (US 20210143172 A1) in view of Gao (US 20220123013 A1).
Regarding claim 3, as shown above, Yun discloses the limitations of claim 2. Yun does not teach that the first and second blocking insulating layers are coupled to each other along sidewalls of the first and second separation patterns if “coupled” is taken to mean “continuously connected.”
Gao teaches, in FIG. 2H, a semiconductor device which comprises “barrier layer” 212 with a top and bottom portion (first and second blocking insulating layers) which are coupled (continuously connected) to each other along sidewalls of “channel dielectric structure” 226 (the examiner notes that the first (leftmost) and second (rightmost) protrusions of the channel dielectric structure that separate “channel layer[s]” 206A and 206C, “tunneling layer sections” 218A and 218C, and “charge trapping layer sections” 220A and 220C constitute separation structures).
It would have been obvious to one having ordinary skill in the art to modify the semiconductor device taught by Yun such that the first blocking insulating layer and the second blocking insulating layer are coupled to each other along sidewalls of the first separation pattern and the second separation pattern. One having ordinary skill in the art is motivated to do so in order to, for example, decrease the complexity of the deposition process of the first and second blocking insulating layers (“The barrier layer 212 can be conformably formed along the sidewall 240 of the channel hole 341” Gao, paragraph 0097), increasing yield and decreasing manufacturing cost.
Regarding claim 10, Gao further teaches, in FIG. 7A, a “dielectric structure[s]” (which separate portions of channel layer sections 206A-D, and are therefore separation structures) which have crescent shapes. The examiner notes that, while FIG. 7A depicts a non-final step in a manufacturing process, the separation structures 306 are present in the final manufacturing step of the embodiment, FIG. 7C.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Yun such that the separation structures have crescent shapes. One having ordinary skill in the art is motivated to do so in order to, for example, form the separation structures with as little as possible material, (the crescent bending inward, as seen in Gao FIG. 7A, as to fill the space in between the adjacent plugs) as to ensure the minimization of manufacturing defects and overspill onto other components.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Uchida (US 20200083248 A1) – Stacked, alternating conductive and insulating layers with a hole, in which there are two “channel films” 21 separated by a “dielectric film wall” 16 which has concave portions relative to the center of the hole.
Ino (US 20220302164 A1) – 3D storage structure comprising an elliptical hole with “crescent moon” (paragraph 0066) channel portions 52a-b, disposed cross an insulating region 70.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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