Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 03/17/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation " the first conductivity type " in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 10, upon which claim 11 depends, is dependent upon claim 7, which is further dependent upon claim 6, which is further dependent on claim 1. Neither claims 10, 7, 6, or 1 recite a first conductivity type, therefore the scope of the claim is unclear. For the purposes of examination, claim 11 will be interpreted as depending upon claim 8.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9, and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mada et al. (US Patent Pub 20180061850 A1).
Regarding Claim 1 Mada teaches a three-dimensional memory device comprising:
a memory die comprising:
an alternating stack of insulating layers and electrically conductive layers, wherein each of the electrically conductive layers comprise a respective horizontally-extending portion and a respective slanted portion that extends at a non-zero and non-orthogonal angle relative to the respective horizontally-extending portion, and wherein each of the slanted portions of the electrically conductive layers has a respective horizontal end surface located within a first horizontal plane (Mada, Fig. 17 teaches an alternating stack of insulating layers 32 and conductive layers 46. Fig. 17 also shows each of 46 has a respective horizontally-extending portion and a respective slanted portion that extends at a non-zero and non-orthogonal angle α relative to the respective horizontally-extending portion. Each of the slanted portions of the electrically conductive layers has a respective horizontal end surface located within a first horizontal plane (the first horizontal plane is located in the same plane as the bottom surface of element 90);
memory openings vertically extending through the alternating stack (Fig. 5C and Fig. 6 show memory openings 49 formed in the stack of alternating layers, subsequently followed by the filling of the memory openings by element 55. Fig. 17 shows the same structure 55 filled in to memory openings 49 (not labeled in fig. 17);
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers (Fig. 17, memory opening fill structures 55 formed in memory opening 49. 55 comprises a vertical semiconductor channel 54 and a vertical stack of memory elements 50/60 located at levels of the electrically conductive layers (see fig. 6A for a diagram showing the memory elements);
and layer contact via structures having a respective end surface that contacts a respective one of the end surfaces of the slanted portions of the electrically conductive layers within the first horizontal plane (Fig. 17, layer contact via structure 86 contacting and end of the slanted portion of 46 within the first horizontal plane (the first horizontal plane is located in the same plane as the bottom surface of element 90). Paragraph 106 teaches that a plurality of 86 can be formed through 90 and contacting 46);
and a logic die comprising a peripheral circuit, wherein the logic die is bonded to the memory die (Fig. 17, logic die 700. Paragraph 0051 and fig. 1 describe the structure of 700).
Regarding Claim 2, Mada teaches the three-dimensional memory device of Claim 1, further comprising a dielectric mesa structure having a slanted sidewall that contacts a bottom surface of a slanted portion of a bottommost insulating layer within the alternating stack (Fig. 17, dielectric mesa 270 has a slanted sidewall that contacts a bottom surface of a slanted portion of a bottommost insulating layer within the alternating stack (paragraph 0055 teaches that an insulating layer 32 can be formed in lieu of 12)).
Regarding Claim 3, Mada teaches the three-dimensional memory device of Claim 2, wherein the slanted sidewall vertically extends from the first horizontal plane to a second horizontal plane including a bottommost surface of the alternating stack (Mada, fig 17, slanted sidewall of 270 extends from first horizontal plane (the first horizontal plane is located in the same plane as the bottom surface of element 90) to the second horizontal plane (the second horizontal plane is located in the same plane as the top surface of element 9), which includes the bottommost surface of the alternating stack (paragraph 0055 teaches that an insulating layer 32 can be formed in lieu of 12).
Regarding Claim 4, Mada teaches the three-dimensional memory device of Claim 2, wherein the dielectric mesa structure comprises a planar top surface located within the first horizontal plane (Fig. 17 teaches a planar top surface of 270 located in the first horizontal plane (the first horizontal plane is located in the same plane as the bottom surface of element 90)).
Regarding Claim 9, Mada teaches the three-dimensional memory device of Claim 1, wherein each of the memory opening fill structures comprises at least one tapered region having a variable lateral extent that decreases along an upward vertical direction (Fig. 5C shows memory opening fill structures 49. Paragraph 0068 teaches 49 are formed by an anisotropic etch step, and that 49 can be tapered, and therefore can be formed such that the at least one tapered region has a variable lateral extent that decreases along an upward vertical direction).
Regarding Claim 12, Mada teaches the three-dimensional memory device of Claim 1, further comprising a lateral isolation trench fill structure having a sidewall that contacts each of the insulating layers and the electrically conductive layers in the alternating stack, wherein the lateral isolation trench fill structure comprises at least one tapered region having a variable lateral extent that increases along an upward vertical direction (Fig. 17, Lateral isolation trench fill structure 74 that contacts each of the insulating layers and the electrically conductive layers in the alternating stack. Figs. 11 and 12 show 74 is formed in trench 79. Paragraph 0089 teaches 79 is formed via an anisotropic etch process, which would produce a tapered trench opening, therefore 74 can be formed tapered and having a variable lateral extent that increases along an upward vertical direction).
Regarding Claim 13, Mada teaches the three-dimensional memory device of Claim 1, further comprising drain contact via structures contacting a top surface of a respective one of the memory opening fill structures within the first horizontal plane (Fig. 17, drain contact via structures 88 contacting a top surface of 63, which is the top surface of respective one of the memory opening fill structures within the first horizontal plane).
Regarding Claim 14, Mada teaches the three-dimensional memory device of Claim 1, wherein the non-zero and non-orthogonal angle is greater than 0.5 degrees and less than 60 degrees (Paragraph 0112 teaches the non-zero and non-orthogonal angle can be between 30 degrees to 75 degrees, which is within the claimed range).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mada et al. (US Patent Pub 20180061850 A1) as applied to claims 1-4, 9, and 12-14 above, and further in view of Okina (US Patent Pub 20220189984 A1).
Regarding Claim 5, Mada teaches the three-dimensional memory device of Claim 2, further comprising:
a through-mesa connection via structure vertically extending through the dielectric mesa structure (Fig. 17, through mesa via connection structure 8P).
Mada fails to specifically teach the through-mesa connection via structure has a variable lateral extent that increases along an upward vertical direction, at least one backside dielectric layer underlying the alternating stack and the dielectric mesa structure, and a backside contact pad embedded in the at least one backside dielectric layer and electrically connected to the through-mesa connection via structure.
However, Okina teaches a three-dimensional memory device having:
a through-mesa connection via structure vertically extending through the dielectric mesa structure and having a variable lateral extent that increases along an upward vertical direction (Okina, fig. 24, through-mesa connection via structure 488, which is formed in a contact via cavity. Paragraph 0135 teaches contact via cavities are formed by an anisotropic etch process. Anisotropic etches lead to tapered openings, therefore 488 can be formed having a variable lateral extent that increases along an upward vertical direction);
at least one backside dielectric layer underlying the alternating stack and the dielectric mesa structure (Fig. 24, backside dielectric layers 769 and 766);
and a backside contact pad embedded in the at least one backside dielectric layer and electrically connected to the through-mesa connection via structure (Fig. 24, backside contact pad 788, which is embedded in 766 and electrically connected to 488).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Okina into the method of Mada by forming the three-dimensional memory device having a through-mesa connection via structure vertically extending through the dielectric mesa structure, and having a variable lateral extent that increases along an upward vertical direction at least one backside dielectric layer underlying the alternating stack and the dielectric mesa structure and a backside contact pad embedded in the at least one backside dielectric layer and electrically connected to the through-mesa connection via structure. The ordinary artisan would have been motivated to modify Mada in the manner set forth above for at least the purpose of improving access speed during programming, reading and erasing operations and improve random access speed during the programming and reading operations due to reduced block size (Okina, paragraph 0172).
Regarding Claim 15, Mada in view of Okina teaches the three-dimensional memory device of Claim 1, wherein:
the memory die further comprises memory-side bonding pads embedded within the memory-side dielectric material layers (Okina, Fig 18 and paragraph 144 teaches memory die 900 having memory-side bonding pads 998 embedded within memory-side dielectric material layers 968);
and the logic die further comprises logic-side bonding pads embedded within logic-side dielectric material layers and bonded to the memory-side bonding pads (Okina, fig. 18 and paragraph 0144 teaches logic die 700 having logic-side bonding pads 798 embedded in logic-side dielectric material layers 768 and bonded to the memory-side bonding pads).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mada et al. (US Patent Pub 20180061850 A1) as applied to claims 1-4, 9, and 12-14 above, and further in view of Baraskar et al. (US Patent Pub 20200388688 A1).
Regarding Claim 6, Mada teaches the three-dimensional memory device of Claim 1, wherein:
the slanted portions of the electrically conductive layers slant upward with an increase in a lateral distance from the memory opening fill structures (Fig. 17 teaches the slanted portions of the electrically conductive layers slant upward with an increase in a lateral distance from the memory opening fill structures).
Mada Fails to teach the memory opening fill structures contact a top surface of a source layer that underlies the alternating stack.
However, Baraskar teaches a three-dimensional memory device wherein the memory opening fill structures contact a top surface of a source layer that underlies the alternating stack (Baraskar, fig. 45D and paragraph 0391 teach a source layer 414 that underlies the alternating stack and wherein the memory opening fill structures 55 contact a top surface of the source layer).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Baraskar into the method of Mada by forming the three-dimensional memory device having memory opening fill structures contact a top surface of a source layer that underlies the alternating stack. The ordinary artisan would have been motivated to modify Mada in the manner set forth above for at least the purpose of reducing feature sizes in a three-dimensional memory device (Baraskar, paragraph 357).
Regarding Claim 7, Mada in view of Baraskar teaches the three-dimensional memory device of Claim 6, wherein each of the vertical semiconductor channels contacts the source layer (Baraskar, Fig. 45D and paragraph 0391 teaches the source layer contacts each of the vertical semiconductor channels 460).
Regarding Claim 8, Mada in view of Baraskar teaches the three-dimensional memory device of Claim 7, wherein:
the vertical semiconductor channel has a doping of a first conductivity type (Baraskar, Fig. 45D and paragraph 0395 teach that the vertical semiconductor channel 460 has a doping of a first conductivity type);
and the source layer comprises a semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type (Baraskar, Fig. 45D and paragraph 0395 teach that the source layer 414 has a doping of a second conductivity type that is opposite of the first conductivity type).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mada in view of Baraskar as applied to claims 6-8 above, and further in view of Son et al. (US Patent Pub 20100254191 A1).
Regarding Claim 10, Mada in view of Baraskar teaches the three-dimensional memory device of Claim 8, wherein each of the memory opening fill structures comprises a horizontal top surface located within the first horizontal plane, (Mada, Fig. 14A teaches a horizontal top surface (top surface of 63) located within the first horizontal plane (the first horizontal plane is located in the same plane as the bottom surface of element 90).
Mada in view of Baraskar fails to teach the memory opening fill structures comprises a horizontal bottom surface located within a second horizontal plane including a bottom surface of a bottommost insulating layer among the insulating layers in the alternating stack.
However, Son teaches a three-dimensional memory device having memory opening fill structures comprising a horizontal bottom surface located within a second horizontal plane including a bottom surface of a bottommost insulating layer among the insulating layers in the alternating stack (Son, Fig. 13F teaches memory opening fill structures 532 having a horizontal bottom surface located within a second horizontal plane (the second horizontal plane is located in the same plane as the bottom surface of element 505). The bottom of 505 (represented in Fig. 13F as 503) is the bottom surface of a bottommost insulating layer among the insulating layers in the alternating stack).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Son into the method of Mada in view of Baraskar by forming the three-dimensional memory device having memory opening fill structures comprising a horizontal bottom surface located within a second horizontal plane including a bottom surface of a bottommost insulating layer among the insulating layers in the alternating stack. The ordinary artisan would have been motivated to modify Mada in view of Baraskar in the manner set forth above for at least the purpose of improving distributed contact area margins for greater reliability (Son, paragraph 0060).
Regarding Claim 11, Mada in view of Baraskar and Son teaches the three-dimensional memory device of Claim 10, wherein each of the memory opening fill structures further comprises a drain region having a doping of a second conductivity type that is an opposite of the first conductivity type and having a top surface located within the first horizontal plane (Baraskar, Fig. 45A and paragraph 0156/0395 teaches drain region 463 have a doping of a second conductivity type that is opposite the first and has a top surface located within the first horizontal plane (the first horizontal plane is represented by the bottom surface of 280). Element 463 is the same drain region as element 63, just represented in a different embodiment).
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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