DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 5 and 10-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/12/2026.
Applicant's election with traverse of Device Embodiment 1, Device Modification A1 and Device Modification A4 in the reply filed on 02/12/2026 is acknowledged. The traversal is on the ground(s) that “In view of the substantial overlap of common elements between alleged Species, Applicants believe that a significant portion of the patents classified in either one of the alleged Species would naturally be found when searching another of the alleged Species. In view of the above, Applicants submit that the search and examination of all the claims may be made without serious burden. Accordingly, Applicants respectfully request the Examiner to reconsider and withdraw the above requirement(s)”. This is not found persuasive because as stated in the Requirement for Restriction/Election mailed on 01/12/2026, the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries). The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the at least one sub-domain comprises…a plurality of first sub-domains…and a second sub-domain…” of Claims 3, 8 and 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because Examiner notes a typographical error on Fig 2B. The cross section region labeled “EA1A” should be “EX1A”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3,8 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 3, the claim recites the limitation “wherein the at least one sub-domain comprises…a plurality of first sub-domains…and a second sub-domain…” in the sixth, seventh and eighth paragraphs of the claim. Looking for support for the at least one sub-domain comprising a first sub-domain and a second sub domain, Examiner notes that Fig 2D of the elected embodiment shows a first and second sub-domain, these being the at least one sub-domain of independent claim 1 but Fig 2D fails to show that either of these regions comprise a first and second sub-domain. Similarly, the specification, in Para [0061, 0063 and 0064] describe a plurality of sub-domains but fails to provide support for the sub-domains to have a first and second sub-domain. For purposes of examination, Examiner interprets “the at least one-sub domain” as “a plurality of sub domains”.
Regarding Claim 8, the claim recites the limitation “wherein the at least one sub-domain comprises…a plurality of first sub-domains…and a second sub-domain…” in the first, second and third paragraphs of the claim. Looking for support for the at least one sub-domain comprising a first sub-domain and a second sub domain, Examiner notes that Fig 2D of the elected embodiment shows a first and second sub-domain, these being the at least one sub-domain of independent claim 1 but Fig 2D fails to show that either of these regions comprise a first and second sub-domain. Similarly, the specification, in Para [0061, 0063 and 0064] describe a plurality of sub-domains but fails to provide support for the sub-domains to have a first and second sub-domain. For purposes of examination, Examiner interprets “the at least one-sub domain” as “a plurality of sub domains”.
Regarding Claim 20, the claim recites the limitation “wherein the at least one sub-domain comprises…a plurality of first sub-domains…and a second sub-domain…” in the third, fourth and fifth paragraphs of the claim. Looking for support for the at least one sub-domain comprising a first sub-domain and a second sub domain, Examiner notes that Fig 2D of the elected embodiment shows a first and second sub-domain, these being the at least one sub-domain of independent claim 1 but Fig 2D fails to show that either of these regions comprise a first and second sub-domain. Similarly, the specification, in Para [0061, 0063 and 0064] describe a plurality of sub-domains but fails to provide support for the sub-domains to have a first and second sub-domain. For purposes of examination, Examiner interprets “the at least one-sub domain” as “a plurality of sub domains”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YOO (US 2018/0358380 A1, hereinafter Yoo ‘380).
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With respect to Claim 1 Yoo ‘380 discloses a semiconductor device (Fig 1-15) comprising:
a stack structure (200, Fig 2A, Para [0024]) comprising a plurality of gate lines (220a-220f, Fig 2A, Para [0028]) and a plurality of insulating patterns (110a-110f, Fig 2A, Para [0029]), the plurality of gate lines (220a-220f) being apart from each other in a vertical direction (vertical direction extending from substrate 101 as shown in Fig 2A and disclosed in Para [0028]), the plurality of insulating patterns (110a-110f) being one-by-one between (Fig 2A and Para [0028] disclose layers 110 and 220 are stacked one-by-one) the plurality of gate lines (220a-220f), the stack structure (200) including a vertical hole (1, Fig 5, Para [0073]) passing therethrough (shown in Fig 5 and disclosed in Para [0073]) in the vertical direction (vertical direction extending from substrate 101);
a channel film (175, Fig 7, Para [0030]) extending in the vertical direction (vertical direction extending from substrate 101) inside the vertical hole (1); and
a composite domain dielectric film (145a/155/165, Fig 2B, Para [0031, 0032 and 0035]) between (shown in Fig 2B) the channel film (175) and the stack structure (200),
wherein the composite domain dielectric film (145a/155/165) comprises,
a main domain (155, Fig 2B, Para [0031]) comprising a ferroelectric material (155 as ferroelectric material disclosed in Para [0031]), the main domain (155) extending in the vertical direction (vertical direction extending from substrate 101) inside the vertical hole (1), and
at least one sub-domain (145a, Fig 2B, Para [0035]) comprising at least one material selected from an anti-ferroelectric material and a paraelectric material (Para [0041] discloses 145a as having an anti-ferroelectric property), the at least one sub-domain (145a) being in contact with (disclosed in Fig 2B) the main domain (155).
With respect to Claim 2 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, and Yoo ‘380 further discloses wherein the composite domain dielectric film (145a/155/165) comprises:
a plurality of first dielectric regions (first dielectric region, as shown in annotated Fig 2B of Yoo ‘380, hereinafter 1DR) facing (1DR facing gate lines 220a-220f disclosed in annotated Fig 2B of Yoo ‘380) the plurality of gate lines (220a-220f) in a lateral direction (horizontal direction as shown in annotated Fig 2B of Yoo ‘380), the plurality of first dielectric regions (1DR) being apart from each other (1DR being apart from each other disclosed in annotated Fig 2B of Yoo ‘380) in the vertical direction (vertical direction extending from substrate 101); and
a plurality of second dielectric regions (second dielectric region, as shown in annotated Fig 2B of Yoo ‘380, hereinafter 2DR) facing (2DR facing insulating patterns 110a-110f disclosed in annotated Fig 2B of Yoo ‘380) the plurality of insulating patterns (110a-110f) in the lateral direction (horizontal direction as shown in annotated Fig 2B of Yoo ‘380), the plurality of second dielectric regions (2DR) being apart from each other (2DR being apart from each other disclosed in annotated Fig 2B of Yoo ‘380) in the vertical direction (vertical direction extending from substrate 101),
wherein the plurality of first dielectric regions (1DR) have different stack structures (as shown in annotated Fig 2B of Yoo ‘380, 1DR has stack structure comprised of 155 and 145a and 2DR has stack structure comprised of 155) and different widths in the lateral direction (annotated Fig 2B of Yoo ‘380 discloses that 1DR has a different width in the lateral direction than 2DR) from the plurality of second dielectric regions (2DR).
With respect to Claim 3 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, and Yoo ‘380 further discloses wherein the composite domain dielectric film (145a/155/165) comprises:
a plurality of first dielectric regions (first dielectric regions, as shown in annotated Fig 2B of Yoo ‘380, hereinafter 1DR) facing (1DR facing gate lines 220a-220f disclosed in annotated Fig 2B of Yoo ‘380) the plurality of gate lines(220a-220f) in a lateral direction (horizontal direction as shown in annotated Fig 2B of Yoo ‘380), the plurality of first dielectric regions being apart from each other (1DR being apart from each other disclosed in annotated Fig 2B of Yoo ‘380) in the vertical direction (vertical direction extending from substrate 101); and
a plurality of second dielectric regions (second dielectric region, as shown in annotated Fig 2B of Yoo ‘380, hereinafter 2DR) facing (2DR facing insulating patterns 110a-110f disclosed in annotated Fig 2B of Yoo ‘380) the plurality of insulating patterns (110a-110f) in the lateral direction (horizontal direction as shown in annotated Fig 2B of Yoo ‘380), the plurality of second dielectric regions (2DR) being apart from each other (2DR being apart from each other disclosed in annotated Fig 2B of Yoo ‘380) in the vertical direction (vertical direction extending from substrate 101),
wherein a width (width of 1DR as shown in annotated Fig 2B of Yoo ‘380, hereinafter W1) of each of the plurality of first dielectric regions (1DR) is less than a width (width of 2DR as shown in annotated Fig 2B of Yoo ‘380, hereinafter W2) of each of the plurality of second dielectric regions (2DR) in the lateral direction (annotated Fig 2B of Yoo ‘380 discloses that width W1 is less than width W2 in the lateral direction), and
the main domain (155) faces (Fig 15 discloses 155 faces gate lines 220a-220f and 110a-110f) each of the plurality of gate lines (220a-220f) and the plurality of insulating patterns (110a-110f) in the lateral direction (horizontal direction as shown in Fig 15), and
wherein the at least one sub-domain (Note the above interpretation of “the at least one sub-domain” as “a plurality of sub-domains”) (145a/165, Fig 2B, Para [0030 and 0035]) comprises,
a plurality of first sub-domains (plurality of 145a, Fig 15, Para [0035]) between the main domain (155) and the plurality of insulating patterns (110a-110f)(plurality of 145a between 155 and 110-110f disclosed in Fig 15), the plurality of first sub-domains (plurality of 145a) being in contact with the main domain (155) and being apart from each other in the vertical direction (vertical direction extending from substrate 101)(plurality of 145a being in contact with 155 and being apart from each other in the vertical direction shown in Fig 15), and
a second sub-domain (165, Fig 2B, Para [0030]) between the main domain (155) and the channel film (175)(165 between 155 and 175 disclosed in Fig 2B), the second sub-domain (165) being in contact with the main domain (155) and extending along the channel film (175) in the vertical direction (vertical direction extending from substrate 101)(165 being in contact with 155 and extending vertically along 175 is disclosed in Fig 2B).
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With respect to Claim 4 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, wherein the main domain (155) comprises:
a plurality of first main domain portions (a plurality of first domain portions 155 shown in annotated Fig 2B_1 of Yoo ‘380) between the channel film (175) and the plurality of gate lines (220a-220f); and
a plurality of second main domain portions (a plurality of first domain portions 155 shown in annotated Fig 2B_1 of Yoo ‘380, here in after SMDP) between the channel film (175) and the plurality of insulating patterns (110a-110f), the plurality of second main domain portions (SMDP) being integrally connected (annotated Fig 2B_1 of Yoo ‘380 discloses FDMP and SDMP are integrally connected) to the plurality of first main domain portions (FMDP), respectively,
wherein a width in a lateral direction (width of FMDP in horizontal direction) of each of the first main domain portions (FMDP) is less than a width in the lateral direction (width of FMDP in horizontal direction) of each of the second main domain portions (SMDP) (annotated Fig 2B_1 of Yoo ‘380 discloses width of FMDP is less than width of SMDP).
With respect to Claim 8 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, and Yoo ‘380 further discloses wherein the at least one sub-domain (Note the above interpretation of “the at least one sub-domain” as “a plurality of sub-domains”) (145a/165, Fig 2B, Para [0030 and 0035]) of the composite domain dielectric film (145a/155/165) comprises (Note Examiner’s interpretation of “the at least one sub-domain of the composite domain dielectric film” as “the composite domain dielectric film”):
a first sub-domain (145a, Fig 2B, Para [0035]) between (145a between 110a-110f and 155 shown in Fig 15) the plurality of insulating patterns (110a-110f) and the main domain (155), the first sub-domain (145a) being in contact with each of the plurality of insulating patterns (110a-110f) and the main domain (155)(145a being in contact with 110a-110f disclosed in Fig 15); and
a second sub-domain (165, Fig 2B, Para [0030]) between (165 between 155 and 175 shown in Fig 15) the main domain (155) and the channel film (175), the second sub-domain (165) being in contact with the main domain (155) and the channel film (175)(165 in contact with 155 and 175 shown in Fig 15),
wherein a width in a lateral direction (width of 155 in horizontal direction as show in Fig 2B) of the main domain (155) is greater than a width in the lateral direction (width of 145a in horizontal direction as shown in Fig 2B and width of 165 in horizontal direction as shown in Fig 2B) of each of the first sub-domain (145a) and the second sub- domain (165)(Fig 2A discloses that the width of 155 in horizontal direction is greater than widths of each of 145a and 165 in the horizontal direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo ‘380 in view of Maeng et al. (US 2021/0359100 A1, hereinafter Maeng ‘100), in view of the following arguments.
With respect to Claim 6 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, and Yoo ‘380 further discloses wherein the main domain (155) of the composite domain dielectric film (145a/155/165) faces each of the plurality of gate lines (220a-220f) and the plurality of insulating patterns (110a-110f) in a lateral direction (horizontal direction as shown in Fig 15)(Fig 15 discloses 155 faces gate lines 220a-220f and insulating patterns 110a-110f in the horizontal direction)
wherein the at least one sub-domain (145a) comprises,
a plurality of first sub-domains (plurality of 145a, Fig 15, Para [0035]) between the main domain (155) and the plurality of insulating patterns (110a-110f)(Fig 15 discloses plurality of 145a between 155 and patterns 110a-110f), the plurality of first sub-domains (plurality of 145a) being in contact with the main domain (155) and being apart from each other in the vertical direction (vertical direction extending from substrate 101)(Fig 15 discloses plurality of 145a being in contact with 155 and being spaced apart from each other in vertical direction), and
a second sub-domain (165, Fig 2B, Para [0030]) between the main domain (155) and the channel film (175)(165 between 155 and 175 shown in Fig 15), the second sub-domain (165) being in contact with the main domain (155) and extending along the channel film (175) in the vertical direction (vertical direction extending from substrate 101)(165 being in contact with 155 and extending vertically along 175 shown in Fig 15), and
wherein each of the plurality of first sub-domains (plurality of 145a) and the second sub- domain comprises an anti-ferroelectric material (Para [0041] discloses 145a as having an anti-ferroelectric property).
But Yoo ‘380 fails to explicitly disclose the second sub- domain comprises an anti-ferroelectric material
Nevertheless, in a related endeavor (Fig 1 of Maeng ‘100), Maeng ‘100 teaches wherein the second sub-domain (111, Fig 1 of Maeng ‘100, Para [0037]) comprises an anti-ferroelectric material (Para [0037] teaches a first paraelectric layer 112 and a second paraelectric layer 111 around a ferroelectric layer 113).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Maeng ‘100’s teaching of the second sub-domain comprises an anti-ferroelectric material into Yoo ‘380’s device. Yoo ‘380 discloses a semiconductor memory device with anti-ferroelectric regions around the channel layer. Yoshimura ‘234 also teaches a semiconductor memory device with anti-ferroelectric regions around the channel layer and discloses using two anti-ferroelectric films around the ferroelectric layer. The ordinary artisan would expect a high likely hood of success and would have been motivated to modify Yoo ‘380 in the manner set forth above, at least, because as Maeng ‘100 teaches in Para [0023] that using two anti-ferroelectric films around a ferroelectric layer enables control over polarization swit6ching to occur in a volatile memory device.
As incorporated, the use of an anti-ferroelectric material in the second sub-domain as taught by Maeng ‘100 would be used as the material of the second sub-domain (165) of Yoo ‘380.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo ‘380 in view of Yoshimura et al. (US 2019/0296234 A1, hereinafter Yoshimura ‘234), in view of the following arguments.
With respect to Claim 7 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, and Yoo ‘380 further discloses wherein the main domain (155) of the composite domain dielectric film (145a/155/165) faces the plurality of gate lines (220a-220f) and the plurality of insulating patterns (110a-110f) in a lateral direction (horizontal direction as shown in Fig 15)(155 facing 220a-220f and 110a-110f in a horizontal direction shown in Fig 15),
wherein the at least one sub-domain (145A) comprises,
a plurality of first sub-domains (plurality of 145a, Fig 15, Para [0035]) between (plurality of 145a between 155 and 110a-110f shown in Fig 15) the main domain (155) and the plurality of insulating patterns (110a-110f), the plurality of first sub-domains (plurality of 145a) being in contact with the main domain (155) and being apart from each other in the vertical direction (vertical direction extending from substrate 101)(plurality of 145a being in contact with 155 and being apart from each other in the vertical direction shown in Fig 15), and
a second sub-domain (165, Fig 2B, Para [0030]) between the main domain (155) and the channel film (175)(165 between 155 and 175 shown in Fig 15), the second sub-domain (165) being in contact with the main domain (155) and extending along the channel film (175) in the vertical direction (vertical direction extending from substrate 101)(165 being in contact with 155 and extending vertically only 175 disclosed in Fig 15), and
wherein each of the plurality of first sub-domains (plurality of 145a) and the second sub- domain (165) comprises a paraelectric material (Para [0041] discloses 145a as paraelectric).
But Yoo ‘380 fails to explicitly disclose wherein the second sub-domain comprises a paraelectric material.
Nevertheless, in a related endeavor (Fig 1-2C and 5 of Yoshimura ‘234), Yoshimura ‘234 teaches wherein the second sub-domain (32, Fig 2B of Yoshimura ‘234, Para [0059]) comprises a paraelectric material (Para [0056] teaches a first paraelectric layer 31b and Para [0059] teaches a second paraelectric layer 32).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yoshimura ‘234’s teaching of the second sub-domain comprises a paraelectric material into Yoo ‘380’s device. Yoo ‘380 discloses a semiconductor memory device with paraelectric regions around the channel layer. Yoshimura ‘234 also teaches a semiconductor memory device with paraelectric regions around the channel layer and discloses using two paraelectric films around the conductive gate lines. The ordinary artisan would expect a high likely hood of success and would have been motivated to modify Yoo ‘380 in the manner set forth above, at least, because as Yoshimura ‘234 teaches in Para [0087] that using two paraelectric films between the conductive gate lines helps to suppress the degradation of the memory characteristics of the memory cell.
As incorporated, the use of a paraelectric material in the second sub-domain as taught by Yoshimura ‘234 would be used as the material of the second sub-domain (165) of Yoo ‘380.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo ‘380 in view of Makala et al. (US 2021/0358931 A1, hereinafter Makala ‘931), in view of the following arguments.
With respect to Claim 9 Yoo ‘380 discloses all limitations of the semiconductor device of claim 1, and Yoo ‘380 further discloses wherein the channel film (175) comprises polysilicon (Para [0033] discloses 175 as silicon), an oxide semiconductor, a two-dimensional (2D) semiconductor material, or a combination thereof.
But Yoo’380 fails to explicitly disclose that the silicon the channel film (175) comprises polysilicon.
Nevertheless, in a related endeavor (Fig 10A-10B of Makala ‘931), Mikala ‘931 teaches the channel film (60L, Fig 10A of Makala ‘931, Para [0115])) comprises polysilicon (Para [0115] discloses silicon of channel layer is polysilicon).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Mikala ‘931’s teaching of the channel film comprises polysilicon into Yoo ‘380’s device. Yoo ‘380 discloses a semiconductor memory device with ferro-electric regions around the channel layer and discloses material options for the channel layer, including silicon. Mikala ‘931 also teaches a semiconductor memory device with ferro-electric regions around the channel layer and discloses that the channel layer is polysilicon. The ordinary artisan would expect a high likely hood of success and would have been motivated to modify Yoo ‘380 in the manner set forth above, at least, because Makala ‘931 teaches the uses of a well-known material that provides the well-known advantage of polysilicon having enhanced electrical performance.
As incorporated, the polysilicon as the material of the channel layer film as taught by Makala ‘931 would be used as the material of the channel layer (175) of Yoo ‘380.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo ‘380 in view of Prasad et al.(US 2021/0066348 A1, hereinafter Prasad ‘348), in view of the following arguments.
With respect to Claim 19 Yoo ‘380 discloses an electronic system (Fig 1-15) comprising:
a main substrate (101, Fig 2A, Para [0024]);
a semiconductor device (20, Fig 2A, Para [0024]) on the main substrate (101); and
wherein the semiconductor device (20) comprises,
a stack structure (200, Fig 2A, Para [0024]) comprising a plurality of gate lines (220a-220f, Fig 2A, Para [0028]) and a plurality of insulating patterns (110a-110f, Fig 2A, Para [0029]), the plurality of gate lines (220a-220f) being apart from each other in a vertical direction (vertical direction extending from substrate 101 as shown in Fig 2A and disclosed in Para [0028]), and the plurality of insulating patterns (110a-110f) being one-by-one between (Fig 2A and Para [0028] disclose layers 110 and 220 are stacked one-by-one) the plurality of gate lines (220a-220f), the stack structure (200) including a vertical hole (1, Fig 5, Para [0073]) passing therethrough (shown in Fig 5 and disclosed in Para [0073]) in the vertical direction (vertical direction extending from substrate 101),
a channel film (175, Fig 7, Para [0030]) extending in the vertical direction (vertical direction extending from substrate 101) inside the vertical hole (1), and
a composite domain dielectric film (145a/155/165, Fig 2B, Para [0031, 0032 and 0035]) between (shown in Fig 2B) the channel film (175) and the stack structure (200), and
wherein the composite domain dielectric film (145a/155/165) comprises,
a main domain (155, Fig 2B, Para [0031]) comprising a ferroelectric material (155 as ferroelectric material disclosed in Para [0031]), the main domain (155) extending in the vertical direction (vertical direction extending from substrate 101) inside the vertical hole (1), and
at least one sub-domain (145a, Fig 2B, Para [0035]) comprising at least one material selected from an anti-ferroelectric material and a paraelectric material (Para [0041] discloses 145a as having an anti-ferroelectric property), the at least one sub-domain (145a) being in contact with (disclosed in annotated Fig 2B of Yoo ‘380) the main domain (155).
But Yoo ‘380 fails to explicitly disclose a controller electrically connected to the semiconductor device on the main substrate,
Nevertheless, in a related endeavor (Prasad ‘348), Prasad ‘348 teaches (Fig 30-32B of Prasad ‘348) a controller (570, Fig 30 of Prasad ‘348, Para [0316]) electrically connected (disclosed in Fig 30 and Para [0316] of Prasad ‘348) to the semiconductor device (550, Fig 30 of Prasad ‘348) on the main substrate (110, Fig 31A of Prasad ‘348, Para [0318])
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Prasad ‘348’s teaching of a controller electrically connected to the semiconductor device on the main substrate into Yoo ‘380’s device. Yoo ‘380 discloses a semiconductor memory device with ferro-electric regions around the channel layer and discloses that the device is controlled in Para [0020]. Prasad ‘348 also teaches a semiconductor memory device with ferro-electric regions and teaches that device in a system. The ordinary artisan would expect a high likely hood of success and would have been motivated to modify Yoo ‘380 in the manner set forth above, at least, because Prasad ‘348 provides details on a controller for the memory system which a person of ordinary skill in the art would be motivated to use as that controller provides teaching of functionality for the memory device.
As incorporated, the controller as taught by Prasad ‘348 would be incorporated to control the semiconductor device (20) of Yoo ‘380.
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With respect to Claim 20 Yoo ‘380 as modified by Prasad ‘348 discloses all limitations of the electronic system of claim 19, and Yoo ‘380 as modified by Prasad ‘348 further discloses wherein
a lateral width (width of 155 as shown in annotated Fig 2B_2 of Yoo ‘380) of the main domain (155) of the composite domain dielectric film (145a/155/165) varies along the vertical direction (vertical direction extending from substrate 101) in the semiconductor device (20),
wherein the at least one sub-domain (see Examiner’s above interpretation of “the at least one sub-domain” as “a plurality of sub-domains”) (145a/165, Fig 2B, Para [0032 and 0035]) of the composite domain dielectric film (145a/155/165) comprises,
a first sub-domain (145a, Fig 2B, Para [0035]) between (145a between 110a-110f and 155 shown in Fig 15) the plurality of insulating patterns (110a-110f) and the main domain (155), the first sub-domain (145a) being in contact with each of the plurality of insulating patterns (110a-110f) and the main domain (155)(145a being in contact with 110a-110f disclosed in Fig 15); and
a second sub-domain (165, Fig 2B, Para [0030]) between (165 between 155 and 175 shown in Fig 15) the main domain (155) and the channel film (175), the second sub-domain (165) being in contact with the main domain (155) and the channel film (175)(165 in contact with 155 and 175 shown in Fig 15), and
wherein the lateral width (width of 155 in horizontal direction as shown in annotated Fig 2B_2 of Yoo ‘380) of the main domain (155) is greater than a lateral width of each of the first sub-domain and the second sub-domain (width of 145a in horizontal direction as shown in annotated Fig 2B_2 of Yoo ‘380 and width of 165 in horizontal direction as shown in annotated Fig 2B_2 of Yoo ‘380).
And Prasad ‘348 further discloses the main substrate (101) further comprises wiring patterns (90, Fig 30 of Prasad ‘348, Para 0315]) configured to electrically connect the semiconductor device (550) to the controller (570), and
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Prasad ‘348’s further teaching of the main substrate further comprises wiring patterns configured to electrically connect the semiconductor device to the controller into Yoo ‘380’s device. Yoo ‘380 discloses a semiconductor memory device with ferro-electric regions around the channel layer and discloses that the device is controlled in Para [0020]. Prasad ‘348 also teaches a semiconductor memory device with ferro-electric regions and teaches that device in a system. The ordinary artisan would expect a high likely hood of success and would have been motivated to modify Yoo ‘380 in the manner set forth above, at least, because Prasad ‘348 provides details on connecting a controller to a memory device which a person of ordinary skill in the art would be motivated to use as that controller provides teaching of functionality for the memory device.
As incorporated, the teaching of the main substrate further comprises wiring patterns configured to electrically connect the semiconductor device to the controller as taught by Prasad ‘348 would be incorporated to connect the controller (570 of Prasad ‘348 as incorporated above) to the semiconductor device (20) of Yoo ‘380 as modified by Prasad ‘348..
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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