DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 02/17/2026.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-16, in the reply filed on 02/17/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/13/2024 and 10/17/2023 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-7 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0093101 A1 (Xie) and further in view of US 2022/0157849 A1 (Lee).
Regarding claim 1, Xie discloses, an integrated circuit device comprising:
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a transistor (600; Fig. 6A; [0051]) comprising first and second source/drain regions (610-1 and 610-2) spaced apart from each other in a horizontal direction (Fig. 6A; [0051] – [0053]);
a backside power distribution network structure (BSPDNS) (1140; backside power distribution network; Fig. 11; [0067]);
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a substrate (100) between the first and second source/drain regions (620-1; [0066] and as annotated on Fig. 11A) and the BSPDNS (1140) (Fig. 11A; [0066]);
a backside contact (1105; electrical contact; Fig. 11A; [0066]) that is in the substrate (100) and is overlapped by the first source/drain region (620-1, right; Fig. 11A);
a placeholder (contact place holder; as annotated on Fig. 11A; [0065]) that is in the substrate (100) and is overlapped by the second source/drain region (left, as annotated on Fig. 11A); and
But Xie fails to teach explicitly, a cavity in the substrate between the backside contact and the placeholder.
However, in analogous art, Lee discloses, a cavity (185; airgap; Fig. 5; [0069]) on the substrate (101),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie and Lee before him/her, to modify the teachings of an integrated circuit device as taught by Xie and to include the teachings of a cavity or airgap as taught by Lee since a cavity or an airgap inside the device reduces the parasitic capacitances. Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Lee while forming an integrated circuit device of Xie.
With this teaching of reducing parasitic capacitance of a device by introducing a cavity from Lee, it is well within the purview of a person with ordinary skill in the art to introduce a cavity in the substrate between the backside contact and the placeholder.
Regarding claim 4, the combination of Xie and Lee discloses, the integrated circuit device of Claim 1, wherein a center of the cavity in the horizontal direction is equidistant from a center of the backside contact in the horizontal direction and a center of the placeholder in the horizontal direction (combining Xie and Lee references would place the cavity in between the backside contact and the placeholder in the horizontal direction; at that point it is possible to place it so that a center of the cavity in the horizontal direction is equidistant from a center of the backside contact in the horizontal direction and a center of the placeholder in the horizontal direction). In MPEP 2144.04 (VI) (C), it is stated that rearrangement of parts is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 5, the combination of Xie and Lee discloses, the integrated circuit device of Claim 1, wherein the cavity is symmetrical with respect to a center line that passes through a center thereof in the horizontal direction and extends in a vertical direction (combining Xie and Lee references would place the cavity symmetrical with respect to a center line that passes through a center thereof in the horizontal direction and extends in a vertical direction). In MPEP 2144.04 (VI) (C), it is stated that rearrangement of parts is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 6, Xie discloses, the integrated circuit device of Claim 1, wherein a thickness of the backside contact (1105) in a vertical direction is equal to a thickness of the placeholder (contact place holder; as annotated on Fig. 11A; [0065]) in the vertical direction (although in Fig. 11, they are shown unequal after further processing, they were originally formed as equal with sacrificial material; Fig. 8A; [0062]). Therefore, it can be considered that the limitation is taught by Xie.
Note: In MPEP 2144.04 (IV) (A), it is stated that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984).
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Regarding claim 7, Xie discloses, the integrated circuit device of Claim 1, wherein a lower surface of the backside contact (1105) and a lower surface of the placeholder (contact place holder; as annotated on Fig. 11A; [0065]) are spaced apart from an upper surface (815; as in Fig. 11a; [0066]) of the substrate (100) in a vertical direction by an equal distance (C and D are equal).
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Regarding claim 10, Xie discloses, the integrated circuit device of Claim 1, wherein the backside contact (1105) is electrically connected to a conductive element (a conductive element of layer 1140) of the BSPDNS (1140) and the first source/drain region (610, right) (Fig. 11a; [0067]).
Regarding claim 11, the combination of Xie and Lee discloses, the integrated circuit device of Claim 1, wherein the cavity (185; airgap; Fig. 5; [0069]) comprises opposing side surfaces curved outwardly (as evident in Fig. 5; Lee Ref.).
Regarding claim 12, the combination of Xie and Lee discloses, the integrated circuit device of Claim 1, wherein the transistor is a first transistor comprising a first channel region (305; nanosheet stack; Fig. 3A; [0040]), the horizontal direction is a first horizontal direction, and the cavity is a first cavity, the first channel region overlaps the first cavity (see the rejection of claim 1 above and the accompanying Figures of Xie and Lee reproduced below), and
the integrated circuit device further comprises:
a second transistor comprising a second channel region (as annotated Xie Fig. 11a), wherein the second transistor is spaced apart from the first transistor in a second horizontal direction perpendicular to the first horizontal direction (combination of Xie and Lee teaches the limitation; see the rejection of claim 1 above and the accompanying Figures of Xie and Lee reproduced below); and
a second cavity (as annotated Lee Fig. 5) that is in the substrate and is spaced apart from the first cavity, wherein the second channel region overlaps the second cavity (combination of Xie and Lee teaches the limitation; see the rejection of claim 1 above and the accompanying Figures of Xie and Lee reproduced below).
Note: In MPEP 2144.04 (VI) (B), it is stated that the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
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Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Xie and Lee as applied to claim 1 and further in view of US 2017/0301794 A1 (Cheng).
Regarding claim 2, Xie discloses, the integrated circuit device of Claim 1, wherein the transistor further comprises a channel region (305; nanosheet stack; Fig. 3A; [0040]) between the first and second source/drain regions (620-1), and
But the combination of Xie and Lee fails to teach explicitly, the channel region overlaps the cavity.
However, in analogous art, Cheng discloses, the channel region (as annotated on Fig. 8B) overlaps the cavity (232; channel recess cavity; Fig. 8B; [0029]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie, Lee and Cheng before him/her, to modify the teachings of an integrated circuit device including cavity as taught by modified Xie and to include the teachings of the channel region overlapping the cavity as taught by Cheng since in MPEP 2144.04 (VI) (C), it is stated that rearrangement of parts is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Cheng while forming an integrated circuit device of Xie.
Regarding claim 3, the combination of Xie, Lee and Cheng discloses, the integrated circuit device of Claim 2, wherein a center of the channel region (as annotated on Fig. 8B) in the horizontal direction and a center of the cavity (232) in the horizontal direction are aligned in a vertical direction (as evident in Fig. 8B; Cheng Ref.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie and Lee as applied to claim 1 and further in view of US 2022/0352309 A1 (Kim).
Regarding claim 8, the combination of Xie and Lee fails to teach explicitly, the integrated circuit device of Claim 1, further comprising: an insulating layer on the substrate, wherein the first and second source/drain regions are in the insulating layer; and a source/drain contact that is in the insulating layer and is electrically connected to the second source/drain region.
However, in analogous art, Kim discloses, the integrated circuit device of Claim 1, further comprising: an insulating layer (190) on the substrate (101), wherein the first and second source/drain regions (150, left and center) are in the insulating layer (190) (Fig. 2A; [0046]); and a source/drain contact (180) that is in the insulating layer (190) and is electrically connected to the second source/drain region (150, center) (Fig. 2A; [0046]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie, Lee and Kim before him/her, to modify the teachings of an integrated circuit device as taught by modified Xie and to include the teachings of an insulating layer on the substrate as taught by Kim since the insulating layers are usually used to separate different source drain regions and contacts. Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Kim while forming an integrated circuit device of Xie.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Xie and Lee as applied to claim 1 and further in view of US 2023/0282722 A1 (Frougier).
Regarding claim 9, the combination of Xie and Lee fails to teach explicitly, the integrated circuit device of Claim 1, wherein the placeholder comprises a material different from the backside contact.
However, in analogous art, Frougier discloses, the integrated circuit device of Claim 1, various contact materials (330 and 316) can be different to allow etch-selectivity (Fig. 16; [0071]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie, Lee and Frougier before him/her, to modify the teachings of an integrated circuit device as taught by Xie and to include the teachings of contact materials can be different as taught by Frougier since when various contacts are needed to be etched differently, then different materials can be used for even similar type of contacts ([0071]). Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Frougier while forming an integrated circuit device of Xie.
With the above teaching from Frougier, it is well within the purview of a person with ordinary skill in the art to use the placeholder comprising a material different from the backside contact.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0093101 A1 (Xie) and further in view of US 2022/0157849 A1 (Lee).
Regarding claim 13, Xie discloses, an integrated circuit device comprising:
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a transistor (600; Fig. 6A; [0051]) comprising a channel region (305; nanosheet stack; Fig. 3A; [0040]) and a source/drain region (610-1 and 610-2) contacting a side surface of the channel region (305);
a backside power distribution network structure (BSPDNS) (1140; backside power distribution network; Fig. 11; [0067]);
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a substrate (100) between the source/drain region (620-1; [0066] and as annotated on Fig. 11A) and the BSPDNS (1140) (Fig. 11A; [0066]);
a backside contact (1105; electrical contact; Fig. 11A; [0066]) that is in the substrate (100) and is between the source/drain region (620-1, right; Fig. 11A) and the BSPDNS (1140); and
a cavity that is in the substrate and is overlapped by the channel region.
But Xie fails to teach explicitly, a cavity that is in the substrate and is overlapped by the channel region.
However, in analogous art, Lee discloses, a cavity (185; airgap; Fig. 5; [0069]) on the substrate (101),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie and Lee before him/her, to modify the teachings of an integrated circuit device as taught by Xie and to include the teachings of a cavity or airgap as taught by Lee since a cavity or an airgap inside the device reduces the parasitic capacitances. Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Lee while forming an integrated circuit device of Xie.
With this teaching of reducing parasitic capacitance of a device by introducing a cavity from Lee, it is well within the purview of a person with ordinary skill in the art to introduce a cavity that is in the substrate and is overlapped by the channel region.
Regarding claim 14, the combination of Xie and Lee discloses, the integrated circuit device of Claim 13, wherein the side surface of the channel region (305; nanosheet stack; Fig. 3A; [0040]; Xie) is one of opposing side surfaces thereof, which are spaced apart from each other in a horizontal direction, and the cavity (185; airgap; Fig. 5; [0069]; Lee) is symmetrical with respect to a center line that passes through a center thereof in the horizontal direction and extends in a vertical direction (combining Xie and Lee references would place the cavity in symmetrical with respect to a center line that passes through a center thereof in the horizontal direction and extends in a vertical direction). In MPEP 2144.04 (VI) (C), it is stated that rearrangement of parts is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 15, Xie discloses, the integrated circuit device of Claim 13, wherein the side surface of the channel region (center 305; nanosheet stack; Fig. 3A; [0040]; Xie) is a first side surface (right), the channel region (305) further comprises a second side surface (left) opposite the first side surface, and the first and second side surfaces are spaced apart from each other in a horizontal direction (Fig. 11A), the source/drain region (as annotated on Fig. 11A, right) is a first source/drain region contacting the first side surface of the channel region, and the transistor further comprises a second source/drain region (as annotated on Fig. 11A, left) contacting the second side surface of the channel region, the integrated circuit device further comprises a placeholder (contact place holder; as annotated on Fig. 11A; [0065]) that is in the substrate and is overlapped by the second source/drain region, and the cavity (185; airgap; Fig. 5; [0069]; Lee Ref.) is between the backside contact and the placeholder (with this teaching of reducing parasitic capacitance of a device by introducing a cavity from Lee, it is well within the purview of a person with ordinary skill in the art to introduce a cavity in the substrate between the backside contact and the placeholder).
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Regarding claim 16, Xie discloses, the integrated circuit device of Claim 13, wherein the side surface of the channel region (center 305; nanosheet stack; Fig. 3A; [0040]; Xie) is a first side surface (right), the channel region (305) further comprises a second side surface (left) opposite the first side surface, and the first and second side surfaces are spaced apart from each other in a horizontal direction (Fig. 11A), and the transistor further comprises a second source/drain region (as annotated on Fig. 11A, left) contacting the second side surface of the channel region, the integrated circuit device further comprises a placeholder (contact place holder; as annotated on Fig. 11A; [0065]) that is in the substrate and is overlapped by the second source/drain region, and a center of the cavity in the horizontal direction is equidistant from a center of the backside contact in the horizontal direction and a center of the placeholder in the horizontal direction (combining Xie and Lee references would place the cavity in between the backside contact and the placeholder in the horizontal direction; at that point it is possible to place it so that a center of the cavity in the horizontal direction is equidistant from a center of the backside contact in the horizontal direction and a center of the placeholder in the horizontal direction). In MPEP 2144.04 (VI) (C), it is stated that rearrangement of parts is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
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Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0310452 A1 (Wu) - A semiconductor device is disclosed comprising first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.
US 2020/0212192 A1 (Xie) - A memory device is disclosed including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.
US 2020/0006478 A1 (Hsu) - A transistor structure is disclosed including a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
03/12/2026