DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “a main board” recited in claim 1 must be shown or the feature canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 13 and 17 are objected to because of the following informalities:
Claim 13 recites “the second detection sections” which should be replace with “the plurality of second detection sections” to avoid antecedent basis issue.
Claim 17 recites “the same length” which should be replace with “a same length” to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 12 recites limitations “the first detection section” and “the second detection section”. Claim 8 (claim 9) recites the limitation “the isolation trenches”. There are insufficient antecedent basis for these limitations in the claim because it is unclear whether “the first detection section” and “the second detection section” relate back to “a plurality of first detection sections” and “a plurality of second detection sections” recited in lines 2-3 of claim 12 respectively or to set forth additional “the first detection section” and “the second detection section”.
Claim 14 recites limitations “the first test pin” (line 7) and “the second test pin” (line 9) that lack antecedent basis in the claim because “a first test pin” and “a second test pin” were not defined by the claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,016,217 (hereinafter Patent’217) in view of Park et al. (US 2018/0158894, hereinafter Park).
Claim 1 of Patent’217 recites a display panel (Col. 12, line 54), comprising:
a display substrate comprising a display area and a non-display area surrounding the display area, wherein the display substrate comprises a substrate, as well as a first bonding portion, a second bonding portion, and a first connection line, which are located on one side of the substrate and located in the non-display area (Col. 12, lines 55-61), wherein:
the first bonding portion comprises a plurality of first pins comprising a first detection pin and a second detection pin (Col. 12, lines 62-64);
the second bonding portion is located on one side of the first bonding portion away from the display area (Col. 12, lines 65-66), the second bonding portion comprises a plurality of second pins comprising a first connection pin and second connection pin (Col. 13, lines 1-3), the first detection pin is electrically connected to the first connection pin, and the second detection pin is electrically connected to the second connection pin (Col. 13, lines 4-5 and 8-9);
the first connection line comprises a first crack detection line arranged around at least a portion of edges of the display area (Col. 13, lines 4-7); and
an integrated circuit chip (Col. 13, lines 10-15) bonded to the first bonding portion, and configured to drive the display substrate to display according to a signal of a main board, and to determine whether there is a crack on an edge of the display substrate according to electric signals of the first detection pin and the second detection pin; and
a circuit board (Col. 13, lines 16-20) bonded to the second bonding portion and configured to transmit a signal of the main board to the integrated circuit chip.
Claim 1 of Patent’217 does not recited the first connection line connects the first connection pin to the second connection pin.
However, Park teaches forming a display panel (Park, Figs. 4, ¶0034-¶0103) comprising a crack detection line (e.g., TCDa/TCDb) (Park, Figs. 4, ¶0038-¶0046) arranged around at least a portion of edges of the display area and a connection line (e.g., signal line TD1 connected to the pad portion PDA through the connection wires CL1/CL2) (Park, Fig. 4, ¶0060) that connects a first connection pin (e.g., a first connection wire CL1 connected to the pad portion PDA) and a second connection pin (e.g., a second connection wire CL2 connected to the pad portion PDA), to provide a test voltage to the crack detection line (e.g., TCDa/TCDb), and to detect defects (e.g., cracks) with increased accuracy in a display panel (Park, Figs. 4, 8, ¶0046, ¶0060, ¶0098).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify claim 1 of Patent’217 by forming a crack detection line including a connection line connected to the connection pad portion as taught by Park to have the display panel, wherein the first connection line connects the first connection pin to the second connection pin, in order to provide an appropriate voltage to a crack detection line arranged around the pixel area to detect defects (e.g., cracks) with increased accuracy in a display panel (Park, ¶0046, ¶0060, ¶0098).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang et al. (hereinafter Zhang) in view of Kimura et al. (US 2017/0031199, hereinafter Kimura) and Park (US 2018/0158894).
With respect to claim 1, Zhang discloses a display panel (e.g., a display device including a display panel 22, see the annotated Figs. 1 and 8 below) (Zhang, Figs. 1-2, 7-8, ¶0006-¶0009, ¶0017-¶0052), comprising:
a display substrate (e.g., a flexible substrate of the display panel 22) (Zhang, Figs. 1-2, 8, ¶0023, ¶0046) comprising a display area (e.g., pixel area 22A) and a non-display area (e.g., a peripheral area around the pixel area 22A and along the peripheral edge of the display 22) (Zhang, Figs. 1-2, 8, ¶0008, ¶0023, ¶0026) surrounding the display area (22A), wherein the display substrate comprises a substrate (e.g., a flexible polymer substrate), as well as a first bonding portion (e.g., bonds 34 including anisotropic conductive bonds or other conductive connections to couple the substrate and the driver circuit 42) (Zhang, Figs. 1-2, 8, ¶0024), a second bonding portion (e.g., connectors 45 to couple display substrate 22 and printed circuit 46) (Zhang, Figs. 1-2, 8, ¶0025), and a first connection line (e.g., peripheral crack detection lines 80-1 and 80-3 connected to the driver circuit 42 including crack detection circuit 44) (Zhang, Figs. 1-2, 8, ¶0026, ¶0042), which are located on one side (e.g., a bottom side) of the substrate and located in the non-display area (e.g., the peripheral area),
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wherein:
the first bonding portion (e.g., bonds 34 including anisotropic conductive bonds or other conductive connections to couple the substrate and the driver circuit 42 having contact pads) (Zhang, Figs. 1-2, 8, ¶0024) comprises a plurality of first pins (e.g., terminals connecting peripheral crack detection lines 80-1 and 80-3 and the crack detection circuit 44) (Zhang, Figs. 1-2, 7-8, ¶0041-¶0042) comprising a first detection pin (e.g., a first terminal connecting the crack detection line 80-1 to the crack detection circuit 44) and a second detection pin (e.g., a second terminal connecting the crack detection line 80-3 to the crack detection circuit 44);
the second bonding portion (45) (Zhang, Figs. 1-2, 8, ¶0024-¶0025) is located on one side of the first bonding portion (34) away from the display area (22A),
the first connection line (e.g., peripheral crack detection lines 80-1/80-3 connected to the driver circuit 42 and the crack detection circuit 44 through a connection line 36) (Zhang, Figs. 1-2, 8, ¶0024-¶0026, ¶0042) connects the driver circuit (42) and the crack detection circuit (44), and comprises a first crack detection line (e.g., 80-1/80-3) arranged around at least a portion of edges of the display area (22A); and
an integrated circuit chip (e.g., the driver circuit 42 including crack detection circuit 44) (Zhang, Figs. 1-2, 8, ¶0024, ¶0025, ¶0028, ¶0042) bonded to the first bonding portion (34), and configured to drive the display substrate to display according to a signal of a control circuit (e.g., a system circuitry 48 for controlling operation of the display device 10), and to determine whether there is a crack on an edge of the display substrate according to electric signals of the first detection pin (e.g., the first terminal connecting the crack detection line 80-1) and the second detection pin (e.g., the second terminal connecting the crack detection line 80-3); and
a circuit board (46) (Zhang, Figs. 1-2, 8, ¶0025, ¶0042) bonded to the second bonding portion (45) and configured to transmit a signal of the control circuit (e.g., a system circuitry 48 for controlling operation of the display device 10) to the integrated circuit chip (42).
Further, Zhang does not specifically disclose that (1) the second bonding portion comprises a plurality of second pins comprising a first connection pin and second connection pin, the first detection pin is electrically connected to the first connection pin, and the second detection pin is electrically connected to the second connection pin; a main board; and a circuit board configured to transmit a signal of the main board to the integrated circuit chip; (2) the first connection line connects the first connection pin to the second connection pin.
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Regarding (1), Kimura teaches forming a display device (see the annotated Figs. 8 and 69 below) (Kimura, Figs. 1A-1B, 4A-4C, 8, 66A-66B, 69, ¶0115-¶0120, ¶0122-¶0144, ¶0341-¶0345, ¶0444-¶0445) comprising an integrated circuit chip (e.g., driver circuit 104 in Figs. 1A-1B
and 8 or 6601 in Figs. 66A-66B) (Kimura, Figs. 1A-1B, 4A-4C, 8, 66A-66B, ¶0123, ¶0137, ¶0343) bonded to a display substrate (e.g., 101 in Figs. 1A-1B and 8 or 6610 in Figs. 66A-66B) and a circuit board (e.g., flexible printed circuit (FPC) 103 in Figs. 1A-1B and 8 or 6609 in Figs. 66A-66B) bonded to the display substrate (101/6610) with the second bonding portion (Kimura, Figs. 1A-1B, 4A-4C, 8, 66A-66B, ¶0129, ¶0137-¶0141, ¶0343) including a plurality of second pins (e.g., connection pads 112/113) and configured to transmit a signal of a main board (e.g., an external the printed wiring board PWB connected to FPC 6609 for transmitting a signal to the driver circuit 6601 through a wire 6608, as in Fig. 66B) (Kimura, Fig. 66A-66B, ¶0343) to the integrated circuit chip (e.g., the driver chip 6601), wherein the plurality of second pins (e.g., connection pads 112/113 in Figs. 4A-4C or 6909/6908 in Fig. 69) (Kimura, Figs. 1A-1B, 4A-4C, 8, 69, ¶0129, ¶0137-¶0141, ¶0444-¶0445) comprises a first connection pin (e.g., connection pads 112 or 6908) and second connection pin (e.g., connection pads 113 or 6909), and the driver circuit (104 or 6903) is electrically connected to the first connection pin (e.g., connection pads 112 or 6908) and the second connection pin (e.g., connection pads 113 or 6909) through the wires (6910/6911/6912). In Kimura, the connection pins including connection pads (112/113 or 6908/6909) to connect the circuit board (e.g., FPC 103/6609) to the display substrate (101/6610) have a specific line-width and a bonding material to reduce contact resistance (Kimura, Figs. 1A-1B, 4A-4C, 8, 69, ¶0013-¶0020, ¶0115-¶0116, ¶0138, ¶0416, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang by bonding the circuit board to the display substrate by using the second bonding portion including a plurality of connection pads (the second connection pins) as taught by Kimura, wherein the circuit board as an external input terminal is connected to a main board for providing a signal to the driver circuit, and wherein the driver circuit is connected to the display substrate and includes the first/second detection pins of Zhang to have the display panel, wherein the second bonding portion comprises a plurality of second pins comprising a first connection pin and second connection pin, the first detection pin is electrically connected to the first connection pin, and the second detection pin is electrically connected to the second connection pin; a main board; and a circuit board configured to transmit a signal of the main board to the integrated circuit chip, in order to provide improved display device having reduced contact resistance between the connection pads and the circuit board (Kimura, ¶0013-¶0020, ¶0115-¶0116, ¶0138, ¶0416, ¶0444).
Regarding (2), Kimura teaches forming the second bonding portion (e.g., connection terminal portion 201) (Kimura, Fig. 20, ¶0178-¶0180) including a plurality of second pins (e.g., pads 112/113) and a first connection line (e.g., wire 2001) surrounding the pixel portion (106), wherein the first connection line (e.g., wire 2001) connects the first connection pin (e.g., pad 113 on one end of the terminal portion 201) and the second connection pin (e.g., pad 113 on another end of the terminal portion 201) to control voltage drop of the electrode of the pixel portion (106).
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Further, Park teaches forming a display panel (see the annotated Fig. 4 below) (Park, Fig. 4, ¶0034-¶0103) comprising a crack detection line (e.g., TCDa/TCDb) (Park, Figs. 4, ¶0038-¶0046) arranged around at least a portion of edges of the display area and a connection line (e.g., signal line TD1 connected to the pad portion PDA through the connection wires CL1/CL2) (Park, Fig. 4, ¶0060) that connects a first connection pin (e.g., a first connection wire CL1 connected to the pad portion PDA) and a second connection pin (e.g., a second connection wire CL2 connected to the pad portion PDA), to provide a test voltage to the crack detection line (e.g., TCDa/TCDb), and to detect defects (e.g., cracks) to increase accuracy of detecting defects in a display panel (Park, Figs. 4, 8, ¶0046, ¶0060, ¶0098).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang by forming the second bonding portion including a plurality of connection pins as a connection terminal portion of Kimura including a first connection pin and a second connection pin, and forming a crack detection line including a connection line connected to the connection pad portion as taught by Park to have the display panel, wherein the first connection line connects the first connection pin to the second connection pin, in order to provide an appropriate voltage to a connection line to prevent defective display; and to provide the crack detection line arranged around the pixel area to detect defects (e.g., cracks) with increased accuracy in a display panel (Kimura, ¶0013, ¶0180; Park, ¶0046, ¶0060, ¶0098).
Regarding claims 2 and 4, Zhang in view of Kimura and Park discloses the display panel according to claim 1. Further, Zhang does not specifically disclose that the second bonding portion further comprises a third connection pin and a fourth connection pin, wherein the third connection pin is connected with the first detection pin through an internal pin and connected with the first connection pin through a connecting wire, and the fourth connection pin is connected with the second detection pin through an internal pin and connected with the second connection pin through a connecting wire (as claimed in claim 2); wherein the connecting wire is independently arranged relative to the circuit board (as claimed in claim 4).
However, Zhang discloses that the second bonding portion (45) (Zhang, Figs. 1-2, 8, ¶0024-¶0026) is connected with first bonding portion (34) through an internal pin (e.g., wiring 36).
Further, Kimura teaches forming the second bonding portion (e.g., connection terminal portion 6907) (Kimura, Fig. 69, ¶0444-¶0445) for bonding a circuit board (e.g., flexible printed circuit (FPC)) to the display substrate (6901), wherein the second bonding portion further comprises a third connection pin (e.g., a third connection pad 6908 connected to the driver circuit 6903) and a fourth connection pin (e.g., a fourth connection pad 6908 connected to the driver circuit 6903), wherein the third connection pin is connected with the driver circuit (6903) through a connecting wire, and the fourth connection pin is connected with the driver circuit (6903) through a connecting wire, such that the third connection pin and the fourth connection pin are connected with the first connection pin and the second connection pin through a connecting wire and driver circuit (6903), and the connecting wire is independently arranged on the display substrate relative to the circuit board (e.g., connecting wire 6608 for transmitting a signal to the driver circuit 6601 is arranged independently relative to the circuit board 6609) (Kimura, Fig. 66B, ¶0343).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park by bonding the circuit board to the display substrate by using the second bonding portion including a plurality of connection pads (the second connection pins), wherein plurality of connection pads (the second connection pins) includes a third connection pad (e.g., a third connection pin) and a fourth connection pad (e.g., a fourth connection pin) connected to the driver circuit through a connecting wire as taught by Kimura, and the second bonding portion is connected with first bonding portion through an internal pin (e.g., wiring 36) as taught by Zhang to have the display panel, wherein the second bonding portion further comprises a third connection pin and a fourth connection pin, wherein the third connection pin is connected with the first detection pin through an internal pin and connected with the first connection pin through a connecting wire, and the fourth connection pin is connected with the second detection pin through an internal pin and connected with the second connection pin through a connecting wire (as claimed in claim 2); wherein the connecting wire is independently arranged relative to the circuit board (as claimed in claim 4), in order to provide an improved display device having reduced contact resistance between the connection pads and the circuit board; and to provide a crack detection circuit in the drive circuit to detect cracks in the flexible display (Kimura, ¶0013-¶0020, ¶0115-¶0116, ¶0138, ¶0416, ¶0444; Zhang, ¶0006-¶0008).
Regarding claim 3, Zhang in view of Kimura and Park discloses the display panel according to claim 2. Further, Zhang does not specifically disclose that the first connection pin and the second connection pin are respectively located at end regions on both sides of the second bonding portion, and the third connection pin and the fourth connection pin are both located between the first connection pin and the second connection pin.
However, Kimura teaches forming the second bonding portion (e.g., connection terminal portion 6907) (Kimura, Fig. 69, ¶0444-¶0445) comprising the first to fourth connection pins (pads), wherein the first connection pin and the second connection pin are respectively located at end regions on both sides of the second bonding portion (6907) to be connected with opposite sides of the drive circuit (6903), and the third connection pin (e.g., connection pad 6908 in the middle of the connection terminal portion 6907) and the fourth connection pin (e.g., another connection pad 6908 in the middle of the connection terminal portion 6907) are both located between the first connection pin and the second connection pin.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park by forming the second bonding portion (as connection terminal portion of Kimura) comprising a plurality of connection pins (the second connection pads) including the first to fourth connection pins (pads) arranged in the second bonding portion as taught by Kimura to have the display panel, wherein the first connection pin and the second connection pin are respectively located at end regions on both sides of the second bonding portion, and the third connection pin and the fourth connection pin are both located between the first connection pin and the second connection pin, in order to provide an improved display device having reduced contact resistance between the connection pads and the circuit board (Kimura, ¶0013-¶0020, ¶0115-¶0116, ¶0138, ¶0416, ¶0444).
Regarding claim 9, Zhang in view of Kimura an Park discloses the display panel according to claim 1. Further, Zhang discloses the display panel, wherein: the first connection line (e.g., peripheral crack detection lines 80-1 and 80-3 connected to the driver circuit 42 including crack detection circuit 44) (Zhang, Figs. 1-2, 8, ¶0024-¶0026, ¶0042) comprises a second lead wire (e.g., horizontal wire connected to the first crack detection line 80-1) connecting one end of the first crack detection line (80-1/80-3) to the first connection pin (e.g., the first terminal connecting the crack detection line 80-1 to the crack detection circuit 44), and a fourth lead wire (e.g., horizontal wire connected to the second crack detection line 80-3) connecting another end of the first crack detection line (80-1/80-3) to the second connection pin (e.g., the second terminal connecting the crack detection line 80-3 to the crack detection circuit 44), wherein orthographic projections of the second lead wire and the fourth lead wire do not overlap (e.g., the horizontal wires are located outside of the bonds 34 connecting the driver chip 42 to the display substrate 22) with an orthographic projection of the first bonding portion (34) on the substrate.
Regarding claim 18, Zhang in view of Kimura and Park discloses the display panel according to claim 1. Further, Zhang discloses a display device (10) (Zhang, Figs. 1-2, 8, ¶0017-¶0022) comprising the display panel according to claim 1.
Claims 5-6, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199) and Park (US 2018/0158894) as applied to claim 1, and further in view of Nam et al. (US 2017/0270842, hereinafter Nam).
Regarding claim 5, Zhang in view of Kimura and Park discloses the display panel according to claim 1. Further, Zhang does not specifically disclose cell test circuit, located between the display area and the integrated circuit chip, wherein an interval region is provided between the cell test circuit and the integrated circuit chip in a direction away from the display area, and the first crack detection line comprises a first detection portion passing through the interval region.
However, Nam teaches forming a display device (Nam, Figs. 1-2, ¶0008-¶0012, ¶0029, ¶0046-¶0077, ¶0081-¶0083) comprising cell test circuit (e.g., Q1) (Nam, Fig. 2, ¶0062-¶0063, ¶0065) located between the display area (DA) (Nam, Fig. 2, ¶0048) and the integrated circuit chip (e.g., driver chip DD) (Nam, Fig. 2, ¶0051), wherein an interval region is provided between the cell test circuit (Q1) and the integrated circuit chip (DD) in a direction away from the display area (DA), and the first crack detection line (e.g., CD1/CD2 and CD3/CD4) (Nam, Fig. 2, ¶0067-¶0071) comprises a first detection portion (e.g., a horizontal portion of the crack sensing lines CD1/CD2 and CD3/CD4 extending between the test circuit Q1 and the drive chip DD) passing through the interval region, to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park by forming a test circuit and crack sensing lines in the non-display region as taught by Nam, wherein the crack sensing lines surround lower/upper and right/left sides of the display region to have the display panel, that further comprises: cell test circuit, located between the display area and the integrated circuit chip, wherein an interval region is provided between the cell test circuit and the integrated circuit chip in a direction away from the display area, and the first crack detection line comprises a first detection portion passing through the interval region, in order to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate (Nam, ¶0005-¶0006, ¶0008-¶0012, ¶0029, ¶0065, ¶0068, ¶0070, ¶0081).
Regarding claim 6, Zhang in view of Kimura, Park, and Nam discloses the display panel according to claim 5. Further, Zhang discloses that the first crack detection line further comprises a second detection portion (e.g., portion 80-1 connected to portion 80-3 with connecting portion 80-2) (Zhang, Fig. 8, ¶0042) arranged around a first portion (e.g., around left edge and partially around an upper edge of the display area) of edges of the display area, but does not specifically disclose a third detection portion arranged around a second portion of edges of the display area, the first portion of edges does not overlap with the second portion of edges or partially overlap with the second portion of edges, and the second detection portion and the third detection portion are respectively connected with both ends of the first detection portion on opposite sides of the interval region.
However, Nam teaches the first crack detection line (CD1/CD2 and CD3/CD4) (Nam, Fig. 2, ¶0067-¶0071) further comprises a second detection portion (CD1/CD2) arranged around a first portion (e.g., around left edge and partially around an upper edge of the display area DA) of edges of the display area (DA) and a third detection portion (CD3/CD4) arranged around a second portion (e.g., around right edge and partially around an upper edge of the display area DA) of edges of the display area (DA), the first portion of edges does not overlap with the second portion of edges, and the second detection portion (e.g., CD1/CD2 around the left edge and partially around the upper edge) and the third detection portion (e.g., CD3/CD4 around the right edge and partially around the upper edge) are respectively connected with both ends of the first detection portion (e.g., the horizontal portion of the crack sensing lines CD1/CD2 and CD3/CD4 at the lower edge of the display area DA) on opposite sides of the interval region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Nam by forming the crack sensing lines surround lower/upper and right/left sides of the display region as taught by Nam to have the display panel, that further comprises: cell test circuit, located between the display area and the integrated circuit chip, wherein a third detection portion arranged around a second portion of edges of the display area, the first portion of edges does not overlap with the second portion of edges, and the second detection portion and the third detection portion are respectively connected with both ends of the first detection portion on opposite sides of the interval region, in order to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate (Nam, ¶0005-¶0006, ¶0008-¶0012, ¶0029, ¶0065, ¶0068, ¶0070, ¶0081).
Regarding claim 15, Zhang in view of Kimura, Park, and Nam discloses the display panel according to claim 6. Further, Zhang discloses the display panel, wherein the second detection portion (e.g., portion 80-1 connected to portion 80-3 with connecting portion 80-2) (Zhang, Fig. 8, ¶0042) surrounding the first portion (e.g., around left edge and partially around an upper edge of the display area) of edges of the display area is in a roundabout shape, but does not specifically disclose that the third detection portion surrounding the second portion of edges of the display area is in a roundabout shape.
However, Zhang teaches that forming the crack detection line (80) (Zhang, Fig. 8, ¶0042) having a roundabout shape with the connection path (80-2) connected to the return line (80-3) provides a crack detection resistor that allows to detect change in the resistance of the crack detection line (80) by the crack detection circuit (44).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Nam by forming the third detection portion of the crack detection line in a roundabout shape as taught by Zhang to have the display panel, wherein the third detection portion surrounding the second portion of edges of the display area is in a roundabout shape, in order to provide a crack detection resistor that allows to detect change in the resistance of the crack detection line (Zhang, ¶0006-¶0008, ¶0042).
Regarding claim 17, Zhang in view of Kimura, Park, and Nam discloses the display panel according to claim 6. Further, Zhang does not specifically disclose that the second detection portion and the third detection portion have substantially the same length.
However, Nam teaches forming the second detection portion (CD1/CD2, arranged the left edge of the display area DA) (Nam, Fig. 2, ¶0067-¶0071) and the third detection portion (CD3/CD4, arranged around the right edge of the display area DA), wherein the second detection portion and the third detection portion have substantially the same length.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Nam by forming the crack sensing lines surround lower/upper and right/left sides of the display region as taught by Nam to have the display panel, wherein the second detection portion and the third detection portion have substantially the same length, in order to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate (Nam, ¶0005-¶0006, ¶0008-¶0012, ¶0029, ¶0065, ¶0068, ¶0070, ¶0081).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199), Park (US 2018/0158894), and Nam (US 2017/0270842) as applied to claim 5, and further in view of Jung (US 2019/0213935) and Cho et al. (US 2016/0133684, hereinafter Cho).
Regarding claim 7, Zhang in view of Kimura, Park, and Nam discloses the display panel according to claim 5. Further, Zhang does not specifically disclose that the display substrate comprises: a semiconductor layer, a first insulation layer, a first gate metal layer, a second insulation layer, and a second gate metal layer, a third insulation layer and a data metal layer located on one side of the substrate and arranged sequentially along a direction away from the substrate; and the first detection portion is located in the data metal layer.
However, Jung teaches forming a display device (Jung, Figs. 2-3, 6, ¶0007-¶0009, ¶0055-¶0087, ¶0101-¶0104) comprising a crack detection lines in the non-display are (NDA) and surrounding a display area (DA), wherein a display substrate (Jung, Figs. 2-3, 6, ¶0060-¶0075) comprises a semiconductor layer (120), a first insulation layer (125), a first gate metal layer (131/132), a second insulation layer (135), and a second gate metal layer (140), a third insulation layer (145) and a data metal layer (151/152) located on one side of the substrate (110) and arranged sequentially along a direction away from the substrate (110); and the first detection portion (CD1/CD2) (Jung, Figs. 2-3, 6, ¶0075, ¶0103) is located in one of the first (131/132) or second (140) gate metal layers, to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate (Jung, ¶0004-¶0005, ¶0007-¶0009, ¶0075, ¶0103-¶0104).
Further, Cho teaches forming a scan line comprising the metal patterns (241 and 242) (Cho, Fig. 4, ¶0007, ¶0103-¶0106, ¶0109) in the same metal layers as the first and second electrodes (51 and 52) of the storage capacitor and the metal pattern (243) in the same metal layer as a data line (16), to ensure sufficient contact area, to reduce the resistance of the scan line (24).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Nam by forming the display substrate comprising a stack of layers to arrange the storage capacitor, transistors, and the crack detection lines as taught by Jung, wherein the crack detection line as the scan line of Cho includes the metal patterns of the storage capacitors and the metal pattern of the data line as taught by Cho to have the display panel, wherein the display substrate comprises: a semiconductor layer, a first insulation layer, a first gate metal layer, a second insulation layer, and a second gate metal layer, a third insulation layer and a data metal layer located on one side of the substrate and arranged sequentially along a direction away from the substrate; and the first detection portion is located in the data metal layer, in order to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate; and to reduce the resistance of the detection line (Jung, ¶0004-¶0005, ¶0007-¶0009, ¶0075, ¶0103-¶0104; Cho, ¶0007, ¶0103, ¶0106, ¶0109).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199), Park (US 2018/0158894), and Nam (US 2017/0270842) as applied to claim 5, and further in view of Kim et al. (US 2018/0158741, hereinafter Kim).
Regarding claim 8, Zhang in view of Kimura, Park, and Nam discloses the display panel according to claim 5. Further, Zhang discloses the display panel, wherein the substrate is a flexible substrate (Zhang, Figs. 1-2, 8, ¶0023), the display area is substantially polygonal (Zhang, Figs. 2 and 8), and the first bonding portion (e.g., bonds 34 including anisotropic conductive bonds or other conductive connections to couple the substrate and the driver circuit 42 having contact pads) (Zhang, Figs. 1-2, 8, ¶0024) is adjacent to one side of the display area (22A); the display substrate further comprises a bending portion (e.g., the tail portion 22T of the flexible display 22 bend around bend axis 28) (Zhang, Figs. 1-2, 8, ¶0030) located on one side of the substrate, but does not specifically disclose a bending portion between the display area and the cell test circuit.
However, Kim teaches forming a display device (Kim, Figs. 1, ¶0004, ¶0006, ¶0039-¶0058) comprising a bent portion (BDA) (Kim, Figs. 1, ¶0047) between the display area (DA) and the test circuits (BCDA and MCDA) (Kim, Figs. 1, ¶0057-¶0058), to provide a reliable display device capable of sensing defects in the no-display area or bending area of the display substrate (Kim, ¶0004, ¶0006, ¶0047, ¶0057-¶0058).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Nam by forming the display substrate comprising a bending portion in a non-display portion as taught by Kim to have the display panel, wherein a bending portion is between the display area and the cell test circuit, in order to provide a reliable display device capable of sensing defects in the no-display area of the display substrate (Kim, ¶0004, ¶0006, ¶0047, ¶0057-¶0058).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199) and Park (US 2018/0158894) as applied to claim 9, and further in view of Jung (US 2019/0213935) and Cho (US 2016/0133684).
Regarding claim 10, Zhang in view of Kimura and Park discloses the display panel according to claim 9. Further, Zhang does not specifically disclose that (1) the display substrate comprises: a semiconductor layer, a first insulation layer, a first gate metal layer, a second insulation layer, and a second gate metal layer, a third insulation layer and a data metal layer located on one side of the substrate and arranged sequentially along a direction away from the substrate; the first pin comprises: a first transmission sub-layer located in the first gate metal layer, and a second transmission sub-layer located in the data metal layer and connected to the first transmission sub-layer through a via hole; and (2) the second pin comprises a single-layer transmission portion located in the data metal layer.
Regarding (1), Jung teaches forming a display device (Jung, Figs. 2-3, 6, ¶0007-¶0009, ¶0055-¶0087, ¶0101-¶0104) comprising a crack detection lines in the non-display are (NDA) and surrounding a display area (DA), wherein a display substrate (Jung, Figs. 2-3, 6, ¶0060-¶0075) comprises a semiconductor layer (120), a first insulation layer (125), a first gate metal layer (131/132), a second insulation layer (135), and a second gate metal layer (140), a third insulation layer (145) and a data metal layer (151/152) located on one side of the substrate (110) and arranged sequentially along a direction away from the substrate (110); and the first detection portion (CD1/CD2) (Jung, Figs. 2-3, 6, ¶0075, ¶0103) is located in one of the first (131/132) or second (140) gate metal layers, to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate (Jung, ¶0004-¶0005, ¶0007-¶0009, ¶0075, ¶0103-¶0104).
Further, Cho teaches forming a scan line comprising the metal patterns (241 and 242) (Cho, Fig. 4, ¶0007, ¶0103-¶0106, ¶0109) in the same metal layers as the first and second electrodes (51 and 52) of the storage capacitor and the metal pattern (243) in the same metal layer as a data line (16), and the first metal pattern (241) is connected to the metal pattern (243) through a via hole, to ensure sufficient contact area to reduce the resistance of the scan line.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park by forming the display substrate comprising a stack of layers to arrange the storage capacitor, transistors, and the crack detection lines as taught by Jung, wherein the first pin of the first bonding portion is arranged as a scan line of Cho and includes the metal patterns of the storage capacitors and the metal pattern of the data line as taught by Cho to have the display panel, wherein the display substrate comprises: a semiconductor layer, a first insulation layer, a first gate metal layer, a second insulation layer, and a second gate metal layer, a third insulation layer and a data metal layer located on one side of the substrate and arranged sequentially along a direction away from the substrate; the first pin comprises: a first transmission sub-layer located in the first gate metal layer, and a second transmission sub-layer located in the data metal layer and connected to the first transmission sub-layer through a via hole, in order to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate; and to reduce the resistance of the first pin (Jung, ¶0004-¶0005, ¶0007-¶0009, ¶0075, ¶0103-¶0104; Cho, ¶0007, ¶0103, ¶0106, ¶0109).
Regarding (2), Kimura teaches forming the second bonding portion (Kimura, Figs. 1A-1B, 4A-4C, 8, 66A-66B, 75, ¶0129, ¶0137-¶0141, ¶0343) including a plurality of second pins (e.g., connection pads 112/113) and configured to transmit a signal of a main board (e.g., an external the printed wiring board PWB connected to FPC 6609 for transmitting a signal to the driver circuit 6601 through a wire 6608, as in Fig. 66B) (Kimura, Figs. 66A-66B, ¶0343) to the integrated circuit chip (e.g., the driver chip 6601), wherein a signal line is provided in the same layer as source/drain wires (7518/7519/7520) (Kimura, Fig. 75, ¶0428), and includes a cooper material having low resistance, such that the second pin (connection pad) comprises a single-layer transmission portion located in the data metal layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park by forming the second bonding portion including a plurality of connection pads (the second connection pins) comprising a copper metal layer provided in the same layer as data metal layer (the source/drain wires)a s taught by Kimura to have the display panel, wherein the second pin comprises a single-layer transmission portion located in the data metal layer, in order to provide a connection line having low resistance (Kimura, ¶0428).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199), Park (US 2018/0158894), Jung (US 2019/0213935), and Cho (US 2016/0133684) as applied to claim 10, and further in view of Saitou et al. (US 2009/0121229, hereinafter Saitou).
Regarding claim 11, Zhang in view of Kimura, Park, Jung, and Cho discloses the display panel according to claim 10. Further, Zhang does not specifically disclose that the second lead wire and the fourth lead wire are located in the second gate metal layer, the second lead wire is connected to the first connection pin through a via hole, and the fourth lead wire is connected to the second connection pin through a via hole.
However, Jung teaches forming the first detection portion (CD1/CD2) (Jung, Figs. 2-3, 6, ¶0075, ¶0103) including lead wires at the low edge of the display area (DA) which are located in one of the first (131/132) or second (140) gate metal layers, to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate (Jung, ¶0004-¶0005, ¶0007-¶0009, ¶0075, ¶0103-¶0104).
Further, Saitou teaches a display device (Saitou, Figs. 1A-1B, 2, ¶0003, ¶0044-¶0053) comprising terminal portion (4) and a drive circuit, and forming reliable connections between the thin film transistors of the drive circuit (Saitou, Figs. 1A-1B, 2, ¶0053) and the terminal portion (4), wherein the metal lines (16) (Saitou, Figs. 1A-1B, 2, ¶0044-¶0045, ¶0051-¶0052) extending out from the terminal portion (4) are connected to the gate lines (11) of the thin film transistors of the drive circuit through a via hole (e.g., 23/24) with the use of continuous conductive film (22) which is brought in contact with the metal lines (16) and gate lines (11), to enhance reliability of electrical connections.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Jung/Cho by forming electrical connections between the terminal portion and gate lines as taught by Saitou, wherein the terminal portion includes the first and second connection pins and the lead wires are located in the second gate metal layer as taught by Jung to have the display panel, wherein the second lead wire and the fourth lead wire are located in the second gate metal layer, the second lead wire is connected to the first connection pin through a via hole, and the fourth lead wire is connected to the second connection pin through a via hole, in order to provide a reliable display device capable of sensing a crack in the no-display area of the display substrate; and to enhance reliability of electrical connections (Jung, ¶0004-¶0005, ¶0007-¶0009, ¶0075, ¶0103-¶0104; Saitou, ¶0003, ¶0052).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199), Park (US 2018/0158894), Jung (US 2019/0213935), and Cho (US 2016/0133684) as applied to claim 10, and further in view of Mandlik et al. (US 2018/0174505, hereinafter Mandlik).
Regarding claim 12, Zhang in view of Kimura, Park, Jung, and Cho discloses the display panel according to claim 10. Further, Zhang does not specifically disclose that the first crack detection line comprises a plurality of first detection sections and a plurality of second detection sections that are alternately provided, wherein the first detection section is located in the second gate metal layer, the second detection section is located in the data metal layer, and the first detection section is connected to the second detection section through a via hole.
However, Park teaches a display panel (Park, Figs. 4, 8, ¶0034-¶0103) comprising the first crack detection line including a plurality of first detection sections (MCDa/MCDb) (Park, Figs. 4, 8, ¶0055-¶0058) and a plurality of second detection sections (TCDa/TCDb) (Park, Figs. 4, 8, ¶0038-¶0046), wherein the first detection section (MCDa/MCDb) is located in the second gate metal layer (e.g., second conductive layer) (Park, Figs. 4, 8, ¶0072), the second detection section (TCDa/TCDb) is located in the data metal layer (e.g., fourth conductive layer) (Park, Figs. 4, 8, ¶0097), and the first detection section (MCDa/MCDb) is connected to the second detection section (TCDa/TCDb) through a via hole (e.g., CNT2) (Park, Figs. 4, 8, ¶0101-¶0103), to provide detection of a defect (e.g., cracks) in a layer below the encapsulation layer (380) and in the encapsulation layer (380) to increase accuracy of detecting defects in a display panel (Park, Figs. 4, 8, ¶0046, ¶0098).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Jung/Cho by forming a crack detection line including a plurality of first detection sections and a plurality of second detection sections as taught by Park to have the display panel, wherein the first crack detection line comprises a plurality of first detection sections and a plurality of second detection sections, wherein the first detection section is located in the second gate metal layer, the second detection section is located in the data metal layer, and the first detection section is connected to the second detection section through a via hole, in order to provide to provide detection of a defect (e.g., cracks) in a layer below the encapsulation layer and in the encapsulation layer to increase accuracy of detecting defects in a display panel (Park, ¶0046, ¶0098).
Further, Mandlik teaches that the peripheral crack detection lines (80A) and (80B) (Mandlik, Figs. 8, 10, ¶0006-¶0009, ¶0060-¶0063) are divided on a plurality of sections connected with bridging portions (RB1 and RB2) to provide a unique crack location corresponding to a specific section by measuring the resistance of each of the plurality of segments.
Thus, a person of ordinary skill in the art would recognize forming a plurality of alternating sections including the first detection sections and the second detection sections of Zhang/Park to provide a unique crack location corresponding to a specific section of the crack detection path by measuring the resistance of each of the plurality of segments as taught by Mandlik.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Jung/Cho by forming a crack detection line including a plurality of first detection sections and a plurality of second detection sections alternately arranged along the crack detection path and connected with bridging portions as taught by Mandlik to have the display panel, wherein the first crack detection line comprises a plurality of first detection sections and a plurality of second detection sections, wherein the first detection section is located in the second gate metal layer, the second detection section is located in the data metal layer, and the first detection section is connected to the second detection section through a via hole, in order to increase accuracy of detecting defects in a display panel by measuring the resistance of each of the plurality of segments (Park, ¶0046, ¶0098; Mandlik, ¶0006-¶0009, ¶0062).
Regarding claim 13, Zhang in view of Kimura, Park, Jung, Cho, and Mandlik discloses the display panel according to claim 12. Further, Zhang discloses the display panel, wherein the display area is substantially polygonal (Zhang, Figs. 2 and 8), the first bonding portion (e.g., bonds 34 including anisotropic conductive bonds or other conductive connections to couple the substrate and the driver circuit 42 having contact pads) (Zhang, Figs. 1-2, 8, ¶0024) is adjacent to one side of the display area (22A), but does not specifically disclose that at least one of the second detection sections is adjacent to a corner of the display area.
However, Park teaches a plurality of second detection sections (TCDa/TCDb) (Park, Figs. 4, 8, ¶0038-¶0046), wherein at least one of the second detection sections (TCDa/TCDb) is adjacent to a corner of the display area (DA).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Jung/Cho/Mandlik by forming a crack detection line including a plurality of first detection sections and a plurality of second detection sections as taught by Park to have the display panel, wherein at least one of the second detection sections is adjacent to a corner of the display area, in order to provide to provide detection of a defect (e.g., cracks) in a layer below the encapsulation layer and in the encapsulation layer to increase accuracy of detecting defects in a display panel (Park, ¶0046, ¶0098).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199), Park (US 2018/0158894), Jung (US 2019/0213935), and Cho (US 2016/0133684) as applied to claim 10, and further in view of Kim et al. (US Patent No. 9,922,585, hereinafter Kim’585).
Regarding claim 14, Zhang in view of Kimura, Park, Jung, and Cho discloses the display panel according to claim 10. Further, Zhang discloses that the second bonding portion (45) (Zhang, Figs. 1, 8, ¶0024-¶0025) is connected to the first bonding portion (34) by a plurality of internal pins (e.g., internal metal traces 36); an external test pin (38) (Zhang, Figs. 1, 8, ¶0028) connected to the first pin of the first bonding portion, but does not specifically disclose a plurality of internal pins which are located in the data metal layer; the plurality of second pins further comprise a first external test pin and a second external test pin, wherein the first external test pin is connected to the first test pin through one internal pin, and the second external test pin is connected to the second test pin through one internal pin.
However, Kim’585 teaches forming a display device (Kim’585, Figs. 3A, 4, 9-10, Col. 1, lines 11-13; Col. 2, lines 59-65; Col. 6, lines 18-52; Col. 7, lines 17-64; Col. 8, lines 12-22) that allows for testing regardless of the shape of the display pane and having a narrow bezel, wherein a test circuit (T1/T2) (Kim’585, Figs. 3A, 4, 9-10, Col. 6, lines 18-52; Col. 7, lines 40-64) having a plurality of external test pins (e.g., external test pads 11-12 and 13-15) of the flexible circuit board (FCP) are connected to a plurality of test pads (e.g., 21-22 and 23-25) of the drive IC and the IC (103) through a plurality of internal pins (e.g., link wires) that allows to detect defects in the link wires and in the IC circuit (103). The test pads (e.g., SD) (Kim’585, Figs. 3A, 4, 9-10, Col. 9, lines 45-67; Col. 10, lines 1-12) are located in data meal layer to connect the test circuit (T1/T2) to the IC drive and the IC (103) through the link wiring.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Jung/Cho by forming a test circuit having a plurality of external test pins connected to the first test pins of the IC circuit as taught by Kim’585 to have the display panel, comprising a plurality of internal pins which are located in the data metal layer, wherein the plurality of second pins further comprise a first external test pin and a second external test pin, wherein the first external test pin is connected to the first test pin through one internal pin, and the second external test pin is connected to the second test pin through one internal pin, in order to provide testing of the display elements regardless of the shape of the display pane and having a narrow bezel, and allow to detect defects in the link wires and in the IC circuit (Kim’585, Col. 1, lines 11-13; Col. 2, lines 59-65; Col. 7, lines 58-64; Col. 10, lines 28-34).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0053455 to Zhang in view of Kimura (US 2017/0031199), Park (US 2018/0158894), and Nam (US 2017/0270842) as applied to claim 15, and further in view of Cho (US 2016/0232826, hereinafter Cho’826).
Regarding claim 16, Zhang in view of Kimura, Park, and Nam discloses the display panel according to claim 15. Further, Zhang does not specifically disclose that at least a portion of the first crack detection line extends in a wave form.
However, Cho’826 teaches forming a display device (Cho’826, Figs. 7-8, 9-10, ¶0008-¶0009, ¶0102-¶0131) comprising a crack detection line (CD1/CD2) arranged at the edges of the display area, wherein at least a portion of a crack detection line (CD1/CD2) (Cho’826, Figs. 7-8, 9-10, ¶0115-¶0131) extends in a zigzag or square-wave form, to improve sensing a crack in the edge of the display area, and thereby preventing the failure of the display device due to the crack.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Zhang/Kimura/Park/Nam by forming a crack detection line in a zigzag or square-wave form as taught by Cho’826 to have the display panel, wherein that at least a portion of the first crack detection line extends in a wave form, in order to improve sensing a crack in the edge of the display area, and thereby preventing the failure of the display device due to the crack (Cho’826, ¶0008, ¶0115, ¶0131).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891