Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 5/26/2026, has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 8-9 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Michalak et al. (US Pub. No. 2019/0305037 A1), hereafter referred to as Michalak.
As to claim 1, Michalak discloses a qubit chip device (fig 1, [0040]) comprising:
a substrate (fig 1, [0041] and 6D, substrate 602);
a superconducting qubit on the substrate (fig 1, [0041] on substrate 602); and
a readout circuit on the substrate and electrically connected to the superconducting qubit (fig 3, [0066]), the readout circuit comprising:
a signal line (322; [0067]) on a surface of the substrate (602);
a ground plate (324, 326, [0067]) on the surface of the substrate (602), the ground plate comprising a pattern forming a coplanar waveguide along the signal line and offset from the signal line (fig 3, coplanar pattern 324/326 offset from 322; [0067], [0125]); and
a conductive bridge (fig 3 shows bridge 330 [0067] and [0105] teaches that a conductive bridge shown in fig 6D can be used instead of the conductive bridge in fig 3) embedded in the substrate (602) and directly connecting two portions of the ground plate in a direction crossing the signal line (fig 6D, conductive bridge including 606 and 608 connect ground plate 624/628 and cross signal line 626; [0105]).
Michalak does not explicitly disclose that the conductive bridge is entirely formed of a same superconductive material.
Instead, Michalak discloses wherein both the bridge extending region (606) and the bridge via region (608) may be provided using one or more dopant implantation techniques similar to each other ([0093]), specifically, the Si or SiGe substrate may be doped with phosphorus (P) or arsenic (As) to doping concentrations ranging 1e18 to 1e21, including all values and ranges therein, e.g. to about 1e20. As a result, doped regions such as the region could be made superconductive, as suitable for superconducting interconnects employed in quantum circuits ([0087]).
As such, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to implant the same dopants with the same doping concentrations to form both the connecting regions and the via regions of the bridge since they are both being implanted into the same substrate and the activation of the dopants can be performed simultaneously such that the entire bridge circuit can be made superconductive as suitable for superconducting interconnects employed in quantum circuits.
As to claim 3, Michalak discloses the qubit chip device of claim 1 (paragraphs above),
wherein the conductive bridge and the ground plate electrically contact with each other (fig 6D and [0105]).
As to claim 8, Michalak discloses the qubit chip device of claim 1 (paragraphs above),
wherein the superconducting qubit ([0052]) comprises:
a first conductive pad and a second conductive pad that are apart from each other on the surface of the substrate (fig 1C, upper and lower pads of capacitor 130); and
a Josephson junction element (132; [0055]) between the first conductive pad and the second conductive pad (upper and lower pads of capacitor 130).
As to claim 9, Michalak discloses the qubit chip device of claim 8 (paragraphs above),
wherein the signal line ([0051]), the ground plate ([0051]), the conductive bridge ([0095]), the first conductive pad, and the second conductive pad each comprise a same superconducting material ([0051]).
As to claim 19, Michalak discloses a planar qubit device (fig 1C) comprising:
a superconducting qubit comprising a Josephson junction electrically connected with a signal line (fig 1C, Josephson junction 132, signal line 322; [0053]; [0067]);
a ground plate (324/326) arranged around the signal line (322/626; [0105]) without contacting the signal line and arranged around the qubit without contacting the qubit (132); and
a bridge crossing (fig 6D, 606/608) under signal line (626) and directly connecting a first portion of the ground plate (624) with a second portion (628) of the ground plate, wherein the first and second portions are across from each relative to the signal line (626).
Michalak does not explicitly disclose that the conductive bridge is entirely formed of a same superconductive material.
Instead, Michalak discloses wherein both the bridge extending region (606) and the bridge via region (608) may be provided using one or more dopant implantation techniques similar to each other ([0093]), specifically, the Si or SiGe substrate may be doped with phosphorus (P) or arsenic (As) to doping concentrations ranging 1e18 to 1e21, including all values and ranges therein, e.g. to about 1e20. As a result, doped regions such as the region could be made superconductive, as suitable for superconducting interconnects employed in quantum circuits ([0087]).
As such, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to implant the same dopants with the same doping concentrations to form both the connecting regions and the via regions of the bridge since they are both being implanted into the same substrate and the activation of the dopants can be performed simultaneously such that the entire bridge circuit can be made superconductive as suitable for superconducting interconnects employed in quantum circuits.
As to claim 20, Michalak discloses the planar qubit device of claim 19 (paragraphs above),
wherein the signal line comprises a wave guide configured to guide a wave read from the qubit ([0067]), and wherein the signal line is connected with the qubit by an antenna pad between the signal line and the Josephson junction (fig 1C, capacitor pads 130 function as antenna pad; see pertinent art section Rosenblatt et al.).
Allowable Subject Matter
Claims 10-12 and 17-18 are allowed.
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the forming of the conductive bridge comprises: forming a trench by etching the substrate; depositing a superconducting material layer in the trench; forming a groove in the superconducting material layer by etching the superconducting material layer; and forming a dielectric layer in the groove, as recited in claim 10; or wherein the conductive bridge comprises niobium nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), or vanadium nitride (VN), as recited in claim 4. Claims 11-12 and 17-18 are allowable because of their dependence on claim 10.
Response to Arguments
Applicant's arguments filed 5/26/2026 have been fully considered but they are not persuasive.
Applicant argued the Michalak reference never states that the dopant-implanted vias result in a same material as the doped lower interconnect and therefore Michalak does not anticipate the amended claim limitations and it would not have been obvious to use the same materials for the dopant of the vias and lower connection region.
Examiner disagrees because as presented above, it would have been obvious to one of ordinary skill in the art to use the same dopant materials with the same doping techniques since the dopant regions are both implanted into the same substrate and are both intended to make a same superconducting connection region of the bridge circuit.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rosenblatt et al. (US Pub. No. 2020/0152853A1), US Pub. No. 2021/0159384A1, US Pub. No. 2021/0359384A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 6/18/2026
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