Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election with traverse of Species I in the reply filed on January 28, 2026 is acknowledged. The traversal is on the ground(s) that there would be no burden in examining all claims and that classification is the same for each of the species. This is not found persuasive. Applicants have not shown that the species are not patentably distinct. Applicants appear to be arguing that same classification means same invention. If such were carried to its logical conclusion there could only be one patent per class and Applicants could be denied a patent on the basis that there is already at least one patent in said class. With regard to the "no burden" argument, it is noted that each distinct invention beyond one is a burden in that it draws the attention of the Examiner to its own requirements. Examination requires focus to follow search leads and patterns of logic in formulating applications of the prior art to that which is claimed. When the Examiner has to pursue several search patterns of logic simultaneously or serially, added burden is presented. In order to examine several species simultaneously or serially, added effort beyond that necessary for one species must be expended. Where the effort is serial and the jobs are different the added burden is obvious. Digging two equal holes of the same size requires twice the effort of digging one hole. Such is an obvious conclusion. It can be argued that some species can be examined simultaneously but such is true only if they are not patentably distinct, that is, if that which applies to any one applies to all others. Where species are patentably distinct each requires separate consideration. Finding references anticipating or making obvious one does not necessarily render the other unpatentable. Having to examine the other constitutes a burden. If the species are not patentably distinct no burden is presented in examining both since if one falls the other falls as well.
The requirement is still deemed proper and is therefore made FINAL.
Claims 5-7 and 13-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and/or species. Applicant timely traversed the restriction (election) requirement in reply filed on January 28, 2026.
Claims 1-4, 8-12 and 16-20 are elected for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-12 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Michalak et al. (US Pub. No. 2019/0305037 A1), hereafter referred to as Michalak.
As to claim 1, Michalak discloses a qubit chip device (fig 1, [0040]) comprising:
a substrate (fig 1, [0041] and 6D, substrate 602);
a superconducting qubit on the substrate (fig 1, [0041] on substrate 602); and
a readout circuit on the substrate and electrically connected to the superconducting qubit (fig 3, [0066]), the readout circuit comprising:
a signal line (322; [0067]) on a surface of the substrate (602);
a ground plate (324, 326, [0067]) on the surface of the substrate (602), the ground plate comprising a pattern forming a coplanar waveguide along the signal line and offset from the signal line (fig 3, coplanar pattern 324/326 offset from 322; [0067], [0125]); and
a conductive bridge (fig 3 shows bridge 330 [0067] and [0105] teaches that a conductive bridge shown in fig 6D can be used instead of the conductive bridge in fig 3) embedded in the substrate (602) and connecting two portions of the ground plate in a direction crossing the signal line (fig 6D, conductive bridge including 606 and 608 connect ground plate 624/628 and cross signal line 626; [0105]).
As to claim 2, Michalak discloses the qubit chip device of claim 1 (paragraphs above),
wherein the conductive bridge comprises a superconducting material ([0095]).
As to claim 3, Michalak discloses the qubit chip device of claim 1 (paragraphs above),
wherein the conductive bridge and the ground plate electrically contact with each other (fig 6D and [0105]).
As to claim 4, Michalak discloses the qubit chip device of claim 3 (paragraphs above),
wherein the conductive bridge comprises niobium nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), or vanadium nitride (VN) ([0095]).
As to claim 8, Michalak discloses the qubit chip device of claim 1 (paragraphs above),
wherein the superconducting qubit ([0052]) comprises:
a first conductive pad and a second conductive pad that are apart from each other on the surface of the substrate (fig 1C, upper and lower pads of capacitor 130); and
a Josephson junction element (132; [0055]) between the first conductive pad and the second conductive pad (upper and lower pads of capacitor 130).
As to claim 9, Michalak discloses the qubit chip device of claim 8 (paragraphs above),
wherein the signal line ([0051]), the ground plate ([0051]), the conductive bridge ([0095]), the first conductive pad, and the second conductive pad each comprise a same superconducting material ([0051]).
As to claim 10, Michalak discloses a method of manufacturing a qubit chip device ([0010]), the method comprising:
forming a conductive bridge having two end portions exposed at a surface of a substrate and a remaining portion embedded in the substrate (fig 6D, conductive bridge 606/608 in the substrate 602);
forming a coplanar waveguide on the surface of the substrate such that both the end portions of the conductive bridge are in contact with a ground plate in the coplanar waveguide (fig 6D, [0105] and [0125]); and
forming a Josephson junction element to be electrically connected with the coplanar waveguide (fig 1C, 132; [0055]).
As to claim 11, Michalak discloses the method of claim 10 (paragraphs above),
wherein the forming of the coplanar waveguide is performed such that the ground plate is capable of making direct electrical contact with both end portions of the conductive bridge (fig 6D, [0105]).
As to claim 12, Michalak discloses the method of claim 11 (paragraphs above),
wherein the conductive bridge comprises niobium nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), or vanadium nitride (VN) ([0095]).
As to claim 17, Michalak discloses the method of claim 10 (paragraphs above),
wherein the forming of the coplanar waveguide comprises forming conductive pads connected to both sides of the Josephson junction element (fig 1C, [0043], [0055]).
As to claim 18, Michalak discloses the method of claim 10 (paragraphs above),
wherein the coplanar waveguide and the conductive bridge each comprise a same superconducting material ([0095], [0103]).
As to claim 19, Michalak discloses a planar qubit device (fig 1C) comprising:
a superconducting qubit comprising a Josephson junction electrically connected with a signal line (fig 1C, Josephson junction 132, signal line 322; [0053]; [0067]);
a ground plate (324/326) arranged around the signal line (322/626; [0105]) without contacting the signal line and arranged around the qubit without contacting the qubit (132); and
a bridge crossing (fig 6D, 606/608) under signal line (626) and electrically connecting a first portion of the ground plate (624) with a second portion (628) of the ground plate, wherein the first and second portions are across from each relative to the signal line (626).
As to claim 20, Michalak discloses the planar qubit device of claim 19 (paragraphs above),
wherein the signal line comprises a wave guide configured to guide a wave read from the qubit ([0067]), and wherein the signal line is connected with the qubit by an antenna pad between the signal line and the Josephson junction (fig 1C, capacitor pads 130 function as antenna pad; see pertinent art section Rosenblatt et al.).
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the forming of the conductive bridge comprises: forming a trench by etching the substrate; depositing a superconducting material layer in the trench; forming a groove in the superconducting material layer by etching the superconducting material layer; and forming a dielectric layer in the groove, as recited in claim 16.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rosenblatt et al. (US Pub. No. 2020/0152853A1), US Pub. No. 2021/0159384A1, US Pub. No. 2021/0359384A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/20/2026