Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/04/2012 and 06/07/2012 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4,19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al, US 20230133595 A1.
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Pertaining to claim 1, Yang teaches ( see fig.7A above) A semiconductor device, comprising: two adjacent memory cells[724], wherein each of the two adjacent memory cells comprises a transistor[726] having a semiconductor body[730], a first terminal[738/ source], a second terminal[738/drain], and a gate terminal[734/gate electrode]; and a conductive structures[ see element 734/ word line between two adjacent transistors 726 and connecting them] between transistors of the two adjacent memory cells [724], the conductive structure[734/ word line between two adjacent transistors 726 ] being in contact with at least one of semiconductor bodies[730] of the transistors [726] of the two adjacent memory cells[724], wherein the conductive structure[734/ word line] is spaced from the first terminal [738/ source] and the second terminal[738/drain] of each of the transistors[726] of the two adjacent memory cells[724] ( see fig.7A above).
Pertaining to claim 2, Yang teaches ( see fig.7A above) . The semiconductor device of claim 1, wherein a working function of the conductive structure[734] ( made of metal see para 0086) is higher than a working function of a semiconductor body [730] ( made of semiconductor material see para 0090) in contact with the conductive structure[734].
Pertaining to claim 3, Yang teaches ( see fig.7A above) The semiconductor device of claim 1, wherein the conductive structure [734] comprises one or more conductive layers that comprise at least one of a metallic layer, a polysilicon layer, a germanium-silicon (GeSi) layer, or a barrier layer ( see para 0086).
Pertaining to claim 4, Yang teaches ( see fig.7A above) The semiconductor device of claim 1, wherein the conductive structure[734/word line] is contact with each of the semiconductor bodies[730] of the transistors[726] of the two adjacent memory cells[724].
Pertaining to claim 19, Yang teaches ( see fig.7A above or 13G) A method of forming a semiconductor device, comprising: forming two adjacent memory cells[724] in a semiconductor substrate[1302], wherein each of the two adjacent memory cells[724] comprises a transistor [726] having a semiconductor body[730], a first terminal [738/ source], a second terminal [738/drain], and a gate terminal [734/gate electrode]; and forming a conductive structure [ see element 734/ word line between two adjacent transistors 726 and connecting them] between transistors [726] of the two adjacent memory cells[724], the conductive structure [734/ word line between two adjacent transistors 726 ] being in contact with at least one of semiconductor bodies[730] of the transistors[726] of the two adjacent memory cells[724], wherein the conductive structure[734/ word line] is spaced from the first terminal [738/source] and the second terminal [738/ drain] of each of the transistors[726] of the two adjacent memory cells[724] ( see fig.7A above).
Allowable Subject Matter
Claim 20 allowed.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Yang et al, US 20230133595 A1 teaches the limitation of “ A semiconductor device, comprising: two adjacent semiconductor bodies; a conductive structure between the two adjacent semiconductor bodies, the conductive structure being in contact with at least one of the two adjacent semiconductor bodies..” but it does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 20 including “two conductive lines on opposite sides of the conductive structure, wherein each of the two conductive lines is coupled to a respective connection structure at an end of the conductive line, wherein the conductive structure is coupled to a corresponding connection structure at an end of the conductive structure, and wherein two adjacent of the respective connection structures coupled to the two conductive lines and the corresponding connection structure coupled to the conductive structure are at: at least one of opposite ends on a same side of the semiconductor device or opposite sides of the semiconductor device.”
Claims 5-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Yang et al, US 20230133595 A1 teaches the limitation of claim1, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 5 including “wherein the semiconductor body comprises opposite ends along a first direction and opposite sides along a second direction perpendicular to the first direction, wherein the first terminal and the second terminal are at the opposite ends of the semiconductor body along the first direction, respectively, and wherein the gate terminal and the conductive structure are at two opposite sides of the semiconductor body, respectively” in combination with the remaining limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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