Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19-25 and 28-38 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dadgar (20070197004).
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Regarding claim 19, Dadgar teaches a method for producing a vertical semiconductor component (please see fig. 6a-6f above; please note that fig. 1 is shown to show the layer numbering), comprising the following steps:
forming a semiconductor layer structure including at least one layer based on gallium nitride (GaN) (fig. 1 and 6a: 110), a vertically lower contact semiconductor layer (fig. 1 and 6a: 106), and at least one vertically higher electrode (fig. 6a: 124) on an intermediate layer (fig. 6a: 108+110) arranged on a substrate (fig. 6a: 104), the substrate being a foreign substrate (par. 108 teaches 104 is an Si wafer);
connecting a carrier material (fig. 6a-6b: 132) on a side of the semiconductor layer structure facing away from the substrate;
removing the substrate (fig. 6c shows removing 104);
lithographically structuring the intermediate layer so that the contact semiconductor layer is exposed in some regions (fig. 6e and par. 145 teaches structuring 108 and exposing portions of 106) and at least a portion of the intermediate layer remains in some regions (fig. 6e and par. 145 teaches 108 remaining in areas); and
forming an electrode (fig. 6f: 136) at least in the exposed regions of the contact semiconductor layer.
Regarding claim 20, Dadgar teaches a method according to claim 19, wherein the substrate is first removed by a grinding process and subsequently by an etching process (par. 145).
Regarding claim 21, Dadgar teaches a method according to claim 20, wherein the etching process is a wet chemical etching process (par. 145).
Regarding claim 22, Dadgar teaches a method according to claim 19, wherein a portion of the intermediate layer is removed in an etching process (please see fig. 6e and 6f).
Regarding claim 23, Dadgar teaches a method according to claim 19, wherein the structuring of the intermediate layer includes a plasma etching process of an unmasked region (par. 145).
Regarding claim 24, Dadgar teaches a method according to claim 19, wherein a metal stack layer, including aluminum and titanium, is formed under the structured intermediate layer (par. 19).
Regarding claim 25, Dadgar teaches a method according to claim 24 wherein the forming of the metal stack layer includes an annealing operation (par. 110 and 125).
Regarding claim 28, Dadgar teaches a method according to claim 19, wherein the electrode formed in the exposed regions of the contact semiconductor layer and the at least one vertically higher electrode together form at least two electrodes arranged vertically one above the other (please see fig. 6f above).
Regarding claim 29, Dadgar teaches a method according to claim 19, wherein the electrode formed in the exposed regions of the contact semiconductor layer and the at least one vertically higher electrode together form three electrodes arranged vertically one above the other (please see fig. 6f above).
Regarding claim 30, Dadgar teaches a method according to claim 19, wherein the electrode formed in the exposed regions of the contact semiconductor layer constitutes a vertically lower electrode that electrically contacts the contact semiconductor layer (please see fig. 6f above).
Regarding claim 31, Dadgar teaches a method according to claim 19, wherein the intermediate layer is configured to compensate for a lattice mismatch between the foreign substrate and the contact semiconductor layer (par. 119 and 129 teaches using 108 as a buffer for growth).
Regarding claim 32, Dadgar teaches a method according to claim 19, wherein, after removal of the substrate, the vertical semiconductor component does not include the foreign substrate (please see fig. 6c).
Regarding claim 33, Dadgar teaches a method according to claim 19, wherein, after structuring of the intermediate layer, the intermediate layer remains arranged vertically below the contact semiconductor layer in some regions (please see fig. 6f).
Regarding claim 34, Dadgar teaches a method according to claim 19, wherein the structuring of the intermediate layer leaves the intermediate layer remaining in an edge region of the vertical semiconductor component (please see fig. 6f).
Regarding claim 35, Dadgar teaches a method according to claim 19, wherein the intermediate layer includes a plurality of individual layers, and wherein at least one of the individual layers remains after the structuring of the intermediate layer (please see fig. 6a and 6f).
Regarding claim 36, Dadgar teaches a method according to claim 19, wherein the at least a portion of the intermediate layer that remains in the some regions after the structuring has a thickness of 2 um- 5 um (par. 83-89).
Regarding claim 37, Dadgar teaches a method according to claim 19, wherein the at least a portion of the intermediate layer that remains in the some regions after the structuring has a thickness of 3 um- 4 um (par. 83-89).
Regarding claim 38, Dadgar teaches a method according to claim 19, wherein the vertical semiconductor component produced by the method is a transistor (par. 91).
Allowable Subject Matter
Claim 26 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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