DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice to Applicants
This action is in response to the Restriction Election filed on 07/21/2026.
Claims 1-20 are pending, with 11-19 currently withdrawn from consideration.
Restriction/Election
The examiner thanks Applicant for their careful consideration of the restriction requirement mailed on 05/21/2026.
Applicant’s election without traverse of Group I (Claims 1-10 & 20) in the reply filed on 07/21/2026 is acknowledged.
Claims 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/21/2026.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The examiner notes that the claim terms “processing circuitry”, “classifier”, and “decision model” all connotate definite structure to one of ordinary skill in the art and thus do not invoke 112(f). The terms “inspection tool” and “review tool” are not positively recited as structure required for the claim, and are also given definitions in paragraphs 0035-0037 of the originally-filed specification, and thus do not invoke 112(f) either.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7, 9, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
Analysis for claim 1 is provided in the following. Claim 1 is reproduced in the following (annotation added):
A computerized system for runtime defect examination on a semiconductor specimen, the system comprising a processing circuitry configured to:
obtain an inspection dataset informative of a group of defect candidates and attributes thereof resulting from examining the semiconductor specimen by an inspection tool;
classify, by a classifier, the group of defect candidates into a plurality of defect classes such that each defect candidate is associated with a respective defect class;
and rank, by a decision model, the group of defect candidates into a total order using a sorting rule, wherein each defect candidate is associated with a distinct ranking in the total order representative of the likelihood of the defect candidate being a defect of interest (DOI),
wherein the decision model is previously trained to learn the sorting rule pertaining to the plurality of defect classes associated with the group of defect candidates and a series of attributes in the inspection data.
Step 1: Does the claim belong to one of the statutory categories? Claim 1 is directed to an apparatus, which is a statutory category of invention (YES).
Step 2A Prong One: Does the claim recite a judicial exception? Parts c and d are regarded as including mental processes that can be practically performed in the human mind. Part c recites using a classifier to associate each defect candidate with a respective defect class; a human can also do this by mentally determining the class for each defect and optionally using pen and paper as an aid. Part d recites using a decision model to rank the defects into a total order using a sorting rule, where each position in the total order is based on the defect’s likelihood of being a “defect of interest”; a human can also perform this by comparing the defects and sorting them, also optionally using pen and paper as an aid (YES).
Step 2A Prong Two: Does the claim recite additional elements that integrate the judicial exception into a practical application? Part a recites a computerized system at a high level of generality and intended use language. Part b recites data gathering of an inspection dataset. Part e recites that the decision model is trained to learn the sorting rule with no further details, which does not integrate the judicial exceptions into a practical application as being trained is considered a necessary feature of decision models as disclosed (NO).
Step 2B: Does the claim as a whole amount to significantly more than the recited exception? The claim as a whole recites a computerized system for defect examination on semiconductor specimens, which is interpreted as intended use language. The claim recites obtaining the inspection dataset via examination, which is interpreted as data gathering in the context of the claim, as this dataset is only used in the claim by the further mental processes. Finally, the claim recites that the decision model is generally trained to learn the sorting rule, which is not interpreted as integrating into a practical application, as any machine learning model, such as the decision model as disclosed, is necessarily trained for its specific purpose (NO). Claim 1 is not eligible.
Similar analysis is applicable to independent claim 20. Claim 20 is not eligible.
Claim 2 recites that the inspection dataset is represented as a tabular dataset, which does not integrate into a practical application. Claim 2 is not eligible.
Claim 3 recites selecting a list of defect candidates from the inspection data to be reviewed by a review tool, in accordance with a review budget of the review tool, which can still be performed mentally. Claim 3 is not eligible.
Claim 4 recites creating a normalized dataset with filtered attributes, by transforming values of attributes thereof into a specific distribution, which is directed to mathematical calculations. The claim further recites evaluating transformation error to determine whether to filter a given attribute form the inspection dataset, which can also be performed mentally. Claim 4 is not eligible.
Claim 5 recites partitioning the dataset into sub-spaces and performing the normalizing and classifying for each sub-space, which is still directed to mathematical calculations and mental processes, respectively. The claim further recites ranking classified defect candidates combined from the plurality of sub-spaces, which is still mentally performable. Claim 5 is not eligible.
Claim 6 recites specific species of classes that the classifier classifies the candidate defects as, which can still be performed mentally. Claim 6 is not eligible.
Claim 7 recites that the classifier is previously trained on training data derived from a subset of defect candidates reviewed by a review tool and has ground-truth defect class attributes; this process of using reviewed, ground-truth training data is considered well-understood, routine, conventional activity in the field of machine learning. Claim 7 is not eligible.
Claims 8 and 10 each recite further unique training details, narrowing the training in step e of claim 1 and thus integrating the judicial exceptions into a practical application. Claims 8 and 10 are eligible.
Claim 9 recites training and training dataset details similar to claim 7. Claim 9 is not eligible.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 9-10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sofer et al. (U.S. Publ. US-2018/0306728-A1) in view of Ma et al. (U.S. Publ. US-2018/0060702-A1).
Regarding claim 1, Sofer discloses a computerized system (see figures 2 and 5) for runtime defect examination on a semiconductor specimen (paragraphs 0001-0008 specify that the invention is directed to semiconductor defect detection), the system comprising a processing circuitry configured to (see figure 5, processors 512 and paragraphs 0115-0118):
obtain an inspection dataset informative of a group of defect candidates and attributes thereof resulting from examining the semiconductor specimen by an inspection tool (first see figure 1, step 124 and paragraph 0038, where an inspection device/tool can be used to determine potential/candidate defects; then see figure 3, step 304 and paragraphs 0060-0061, where the potential defects are obtained for further processing);
classify, by a classifier, the group of defect candidates into a plurality of defect classes such that each defect candidate is associated with a respective defect class (see figure 3, step 308 and paragraphs 0062-0067, where the potential defects are first clustered into a first cluster based on physical proximity; see figure 3, steps 312-332 and paragraphs 0068-0085, where the defects in the first cluster can be classified at step 320, and the remaining defects are separately clustered and classified at step 316);
and rank, by a decision model, the group of defect candidates into a total order using a sorting rule, wherein each defect candidate is associated with a distinct ranking in the total order (see figure 3, step 336 and paragraphs 0086-0087, where the classified defects from the clusters are then sorted, as detailed in figure 4; see figure 4, steps 404-412 and paragraphs 0087-0099, where the potential defects in each cluster are sorted according to their class probabilities, and then merged into one sorted list) representative of the likelihood of the defect candidate being a defect of interest (DOI) (paragraphs 0069-0070 specify that the probabilities can represent the likelihood of the defects being true defects),
Sofer fails to disclose wherein the decision model is previously trained to learn the sorting rule pertaining to the plurality of defect classes associated with the group of defect candidates and a series of attributes in the inspection data. More specifically, Sofer merely fails to disclose any training details of the decision model.
Pertaining to the same field of endeavor, Ma discloses wherein the decision model is previously trained to learn the sorting rule pertaining to the plurality of defect classes associated with the group of defect candidates and a series of attributes in the inspection data (see figure 2 and paragraphs 0026-0027, 0036-0046, where a machine learning model can be trained to classify and rank/sort detected defects based on known defect types; figure 3B and paragraphs 0026, 0046 specify particular training updates for the ranking model; paragraphs 0025, 0030 specify that the classification and ranking are based on attributes such as position and defect types).
Sofer and Ma are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Ma into Sofer by training Sofer’s decision model because doing so ensures model accuracy for automatic defect classification (see Ma paragraph 0044).
Regarding claim 3, Sofer in view of Ma discloses wherein the processing circuitry is further configured to select, from the inspection dataset, a list of defect candidates to be reviewed by a review tool, the list of defect candidates selected in accordance with a review budget of the review tool based on the distinct ranking thereof (see Sofer figure 4, step 416 and paragraphs 0099-0104, where a subset of the merged, sorted list of potential defects is selected for further review, such as by selecting the highest probability defects; paragraph 0104 specifies that the selected defects are further examined by a review tool; paragraphs 0100, 0102, 0107 specify that only a limited number of defects can be selected based on review budget constraints).
Regarding claim 7, Sofer fails to disclose the limitations of claim 7.
Pertaining to the same field of endeavor, Ma discloses wherein the classifier is previously trained based on training data derived from a subset of defect candidates that is reviewed by a review tool and has an attribute indicative of ground truth defect classes thereof (see paragraph 0033, where a supervised training method for the overall model uses a training defect set with ground-truth class labels; figure 3A and paragraph 0045 specify particular training updates for the classifier model).
Sofer and Ma are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Ma into Sofer by training Sofer’s classifier because doing so ensures model accuracy for automatic defect classification (see Ma paragraph 0044).
Regarding claim 9, Sofer fails to disclose the limitations of claim 9.
Pertaining to the same field of endeavor, Ma discloses wherein the decision model is trained using a training dataset informative of a group of defect candidates and attributes thereof resulting from examining one or more semiconductor specimens by at least an inspection tool and a review tool, the attributes comprising a first attribute indicative of defect classes of the group of defect candidates generated by the classifier, the training dataset comprising a subset of defect candidates that is reviewed by the review tool and has a second attribute indicative of ground truth defect classes thereof (see paragraph 0033, where a supervised training method for the overall model uses a training defect set with ground-truth class labels; paragraph 0024 specifies that the images can be obtained from inspection/review tools such as SEMs).
Sofer and Ma are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Ma into Sofer by using a training dataset with ground-truth classes because doing so ensures model accuracy for automatic defect classification (see Ma paragraph 0044).
Regarding claim 10, Sofer discloses first attribute (see figure 3, step 336 and paragraphs 0086-0087, where the classified defects from the clusters are then sorted, as detailed in figure 4);
for each subset of defect candidates, identifying one or more attributes to be used for sorting the defect candidates within the subset so as to have a sorted subset of defect candidates in accordance with the ground truth defect classes thereof (see figure 4, steps 404-408 and paragraphs 0087-0089, where the potential defects in each cluster/subset are separately sorted);
and sorting between multiple sorted subsets to have all defect candidates
Sofer fails to disclose the limitations indicated via strikethrough above. In other words, Sofer does disclose the above process of modifying a dataset, just not specifically executing said process on a training dataset with ground-truth values during training.
Pertaining to the same field of endeavor, Ma discloses training a machine learning model to rank/sort semiconductor defects using a ground-truth training dataset (see paragraph 0033, where a supervised training method for the overall model uses a training defect set with ground-truth class labels; in combination with Sofer, this would yield the predictable result of Sofer's model performing the same actions on a ground-truth training dataset instead of a runtime dataset).
Sofer and Ma are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Ma into Sofer by applying Sofer’s methods in figures 3 and 4 to a training dataset during training because doing so ensures model accuracy for automatic defect classification (see Ma paragraph 0044).
Regarding claim 20, Sofer discloses a non-transitory computer readable storage medium tangibly embodying a program of instructions that, when executed by a computer (see figure 5, memory 504, processors 512 and paragraphs 0118-0119), cause the computer to perform a method of defect examination on a semiconductor specimen, the method comprising (paragraphs 0001-0008 specify that the invention is directed to semiconductor defect detection).
The remainder of claim 20 recites steps identical to those of claim 1. Therefore, Sofer in view of Ma discloses claim 20 as applied to claim 1 above.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sofer et al. (U.S. Publ. US-2018/0306728-A1) in view of Ma et al. (U.S. Publ. US-2018/0060702-A1), and further in view of Leu et al. (U.S. Publ. US-2021/0231584-A1).
Regarding claim 2, Sofer in view of Ma fails to teach the limitations of claim 2.
Pertaining to the same field of endeavor, Leu discloses wherein the inspection dataset is represented as a tabular dataset (see figure 3C and paragraph 0037, where each known defect and its attributes can be represented in a table).
Sofer and Leu are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Leu into Sofer and Ma by representing the inspection dataset in a tabular form because doing so allows for tracking defect coordinates during design coordinate conversions (see Leu paragraph 0038).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Sofer et al. (U.S. Publ. US-2018/0306728-A1) in view of Ma et al. (U.S. Publ. US-2018/0060702-A1), and further in view of Lenhard et al. (U.S. Publ. US-2022/0122864-A1).
Regarding claim 4, Sofer in view of Ma fails to teach the limitations of claim 4.
Pertaining to the same field of endeavor, Lenhard discloses wherein the processing circuitry is further configured to normalize the inspection dataset by transforming values of each given attribute of at least some of the attributes into a specific distribution (see figure 2, step 210 and paragraph 0039, where inspection datasets including defect data can be normalized),
and evaluate transformation error of the transformation to determine whether to filter the given attribute from the inspection dataset, giving rise to a normalized dataset with filtered attributes each having normalized values (paragraph 0039 specifies that data cleaning/filtering can include removing outliers).
Sofer and Lenhard are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Lenhard into Sofer and Ma by normalizing and filtering the data because doing so allows for representing wide datasets in a common scale without distorting values (see Lenhard paragraph 0039).
Regarding claim 5, Sofer in view of Ma discloses wherein the processing circuitry is further configured to partition the inspection dataset into a plurality of sub-spaces based on one or more attributes (see Sofer figure 3, step 308 and paragraphs 0062-0067, where the potential defects are first clustered into a first cluster based on physical proximity, which is an instance of an attribute, and then the remaining defects are separately clustered at step 316),
and perform the (see Sofer figure 4, steps 404-412 and paragraphs 0087-0099, where the potential defects in each cluster are sorted according to their class probabilities, and then merged into one sorted list).
Sofer in view of Ma fails to disclose perform the normalizing and classifying for each sub-space (emphasis added via underline).
Pertaining to the same field of endeavor, Lenhard discloses performing normalizing for each sub-space (see above citations to claim 4).
Sofer and Lenhard are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Lenhard into Sofer and Ma by using Lenhard’s normalization for each sub-space because doing so allows for representing wide datasets in a common scale without distorting values (see Lenhard paragraph 0039).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sofer et al. (U.S. Publ. US-2018/0306728-A1) in view of Ma et al. (U.S. Publ. US-2018/0060702-A1), and further in view of Wu et al. (U.S. Publ. US-2014/0072203-A1).
Regarding claim 6, Sofer in view of Ma discloses wherein the plurality of classes comprises DOIs, nuisances (Sofer paragraph 0028 specifies that the classes include real defects / DOIs and nuisances),
Sofer in view of Ma fails to disclose unknown and do not care (DNC).
Pertaining to the same field of endeavor, Wu discloses unknown and do not care (DNC) (see paragraph 0024, where classified defect types can include DOIs, nuisances, unknown types, and types the user does not care about).
Sofer and Wu are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Wu into Sofer and Wu by including unknown and DNC classifications because doing so allows for suppressing defect types that the user does not care about for inspection (see Wu paragraph 0024).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sofer et al. (U.S. Publ. US-2018/0306728-A1) in view of Ma et al. (U.S. Publ. US-2018/0060702-A1), and further in view of Moioli et al. (U.S. Publ. US-2020/0134809-A1).
Regarding claim 8, Sofer in view of Ma fails to teach the limitations of claim 8.
Pertaining to the same field of endeavor, Moioli discloses wherein the training data is derived by clustering the subset of defect candidates into a plurality of clusters based on values of inspection attributes of the defect candidates, and including at least the plurality of clusters of defect candidates in the training data (paragraph 0003 first defines a wafer defect map or WDM as sets of coordinates/attributes of identified defects; then see figure 2 and paragraph 0035, where training data can include different ground-truth cluster classes of WDMs).
Sofer and Moioli are considered analogous art, as they are both directed to semiconductor defect detection. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the teachings of Moioli into Sofer and Ma by using clustered training datasets because doing so allows for training a model to identify different defect types and causes (see Moioli paragraphs 0035-0037).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS JOHN HELCO whose telephone number is (703)756-5539. The examiner can normally be reached on Monday-Friday from 9:00 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Bella, can be reached at telephone number 571-272-7778. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS JOHN HELCO/Examiner, Art Unit 2667 /MATTHEW C BELLA/Supervisory Patent Examiner, Art Unit 2667
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