Prosecution Insights
Last updated: July 17, 2026
Application No. 18/488,931

QUANTUM DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Oct 17, 2023
Priority
Jun 28, 2021 — CN 202110718555.X +2 more
Examiner
STEPHENSON, KENNETH STEPHEN
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Origin Quantum Computing Technology (Hefei) Co. Ltd.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
5 granted / 7 resolved
+3.4% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
26 currently pending
Career history
46
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
65.8%
+25.8% vs TC avg
§102
14.5%
-25.5% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 4 – 6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6 March 2026. Applicant's election with traverse of Species I, as presented in at least Fig. 3a & 3b, in the reply filed on 6 March 2026 is acknowledged. The traversal is on the ground(s) that “no additional search or examination will be imposed by present examination of the non-elected claims 4-6, i.e., the non-elected Species II”, as stated on Pag. 6 of the aforementioned remarks, which Applicant supports with an argument regarding the working principle of the claimed quantum chip being unaffected by the presence or absence of the claimed “via holes”. The Examiner respectfully disagrees and does not find the above persuasive because the claimed “via holes”, which distinguish the nonelected species from the elected species, are elements found in a separate CPC area, i.e. H10W 20/0238, compared to the CPC are in which the elected species may be found, i.e. H10N 60, and H10N 69. Further, the Examiner has provided an explanation of the burden of search in the previous Office Action on Pag. 2. Further still, Applicant’s argument does not regard a burden of search as described by MPEP 808.02. The requirement is still deemed proper and is therefore made FINAL. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. With regard to the rejection of Claim 1 under 35 U.S.C. 102(a)(1) as being anticipated by YANG (CN 215008192 U), Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Regarding Claim 1, The feature “signal connector” is recited. However, no such feature is shown in the drawings. Regarding Claim 7, The feature “superconducting element” is recited. However, no such feature is shown in the drawings. Regarding Claim 9, The features “the second base is flipped onto the package substrate, and the first base is flipped onto the second base” are recited. However, no such features are shown in the drawings. Regarding Claim 10, The features “a plurality of package substrates are provided, and wherein the plurality of package substrates are stacked upon each other, and the lead-out segment of each of the package substrates is electrically connected to the connecting segment corresponding to the lead-out segment” are recited. However, no such features are shown in the drawings. Regarding Claim 11, The feature “signal connector” is recited. However, no such feature is shown in the drawings. Regarding Claim 12, The features “An electronic device, comprising: a package assembly; a signal connector, wherein the signal connector is installed on the package assembly; and the quantum device according to claim 1, wherein the quantum device is provided in the package assembly, and the lead-out signal line is electrically connected to the signal connector” are recited. However, no such features are shown in the drawings. Therefore, the above feature(s) must be shown or canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: QUANTUM DEVICE WITH FLIP-CHIP BALL GRID ARRAY. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 3, 7, & 9 – 12 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by ROBERTS (US 20190273197 A1). Regarding Claim 1, ROBERTS discloses: A quantum device (Fig. 3: 130), comprising: a quantum chip (Fig. 2: 111; Fig. 3: 100; Par. 55), wherein a signal transmission element (STE) and (Fig. 2: 112, 114, or 124, respectively; denoted above and hereinafter as STE) a connecting segment (CSG) electrically connected to the signal transmission element (Fig. 2: 120, 122, or 126, respectively; denoted above and hereinafter as CSG) (STE) are formed on the quantum chip (111); (As seen in Fig. 2) a package substrate (Fig. 3: 134), wherein a lead-out segment (Fig. 3: 150) and a lead-out signal line (Fig. 3: 152; Par. 58) configured to be electrically connected to a signal connector (Fig. 3: 158) are formed on the package substrate (134), and the lead-out signal line (152) is electrically connected to the lead-out segment (150); and a ball grid array (Fig. 3: 156) configured to electrically connect the connecting segment (Fig. 2: CSG; Fig. 3: 140; Par. 57) to the lead-out segment (150) corresponding to each other. (As seen in Fig. 3) Regarding Claim 2, ROBERTS discloses: The quantum device according to claim 1, wherein a surface of the connecting segment (140) in contact with the ball grid array (156) is higher than a surface of the quantum chip (100). (As seen in Fig. 3) Regarding Claim 3, ROBERTS discloses: The quantum device according to claim 2, wherein the surface of the connecting segment (140) in contact with the ball grid array (156) is a flat plane or an arc-shaped convex surface. (As seen in Fig. 3) Regarding Claim 7, ROBERTS discloses: The quantum device according to claim 1, wherein the quantum chip (111) comprises: a first base (BSE1), wherein (Fig. 2: 111 inside dashed box; denoted above and hereinafter as BSE1) a first segment (SGT1) of the signal transmission element (STE), and (Fig. 2: portion of STE strictly inside BSE1; denoted above and hereinafter as SGT1.) a qubit (Fig. 2: 102) and a read resonant cavity (Fig. 2: 118) coupled to each other are formed on the first base (BSE1), and the first segment (SGT1) is coupled to the qubit (102) or the read resonant cavity (118); (As seen in Fig. 2) a second base (BSE2), wherein (Fig. 3: 132 & Fig. 2: 111 outside dashed box; denoted above and hereinafter as BSE2.) a second segment (SGT2) of the signal transmission element (STE) is formed on the second base (BSE2); and (Fig. 2: portion of STE strictly inside BSE2; denoted above and hereinafter as SGT2.) a superconducting element (SCE) configured to electrically connecting the first segment (SGT1) to the second segment (SGT2). (Fig. 2: portion of STE in both BSE1 & BSE2, crossing dashed box; denoted above and hereinafter as SCE.) (Par. 37, 48, & 50 teach the entirety of STE—and, thus, portion SCE—may be made of superconducting materials.) Regarding Claim 9, ROBERTS discloses: The quantum device according to claim 7, wherein the second base (BSE2) is flipped onto the package substrate (134), and the first base (BSE1) is flipped onto the second base (BSE2). The language, term, or phrase "the second/first base is flipped onto the package substrate/second base" is directed towards the process of making “the quantum device”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product, per se, which must be determined in a "product by process" claim not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the second/first base is flipped onto the package substrate/second base” only requires “the second/first base is on the package substrate/second base”, which does not distinguish the instant invention from the known invention of ROBERTS, who teaches the structure as claimed. (As BSE2 comprises 132, BSE2 is clearly on 134, as seen in Fig. 3. Also, as BSE1 comprises a portion of 111—and, thus, a portion of 100—BSE1 is clearly on 132. Therefore, BSE1 is clearly on BSE2, as seen in Fig. 3.) Regarding Claim 10, ROBERTS discloses: The quantum device according to claim 1, wherein a plurality of package substrates (Fig. 10: 1326 & 1332) are provided, and (Par. 110 discloses “1326 and 1332 may take the form of…130 [e.g. Fig. 3]…and may include a SC qubit device die 132 coupled to a package substrate 134”.) wherein the plurality of package substrates (1326 & 1332) are stacked upon each other, and (As seen in Fig. 10) the lead-out segment (Fig. 3: 150) of each of the package substrates (1326 & 1332) is electrically connected to the connecting segment (Fig. 3: 140) corresponding to the lead-out segment (Fig. 3: 150). (As 1326 and 1332 may both take the form of 130 in Fig. 3, these limitations are satisfied.) Regarding Claim 11, ROBERTS discloses: A manufacturing method for a quantum device (Fig. 3: 130), comprising: providing a quantum chip (Fig. 2: 111; Fig. 3: 100; Par. 55), wherein a signal transmission element (STE, as defined for Claim 1) and a connecting segment (CSG, as defined for Claim 1) electrically connected to the signal transmission element (STE) are formed on the quantum chip (111); (As seen in Fig. 2) providing a package substrate (Fig. 3: 134), wherein a lead-out segment (Fig. 3: 150) and a lead-out signal line (Fig. 3: 152; Par. 58) configured to be electrically connected to a signal connector (Fig. 3: 158) are formed on the package substrate (134), and the lead-out signal line (152) is electrically connected to the lead-out segment (150); and(As seen in Fig. 3) forming a ball grid array (Fig. 3: 156) to electrically connect the connecting segment (CSG) to the lead-out segment (150) corresponding to the connecting segment (CSG). (As seen in Fig. 3) Regarding Claim 12, ROBERTS discloses: An electronic device, comprising: a package assembly (Fig. 10: 1300); a signal connector (Fig. 3: 158; Fig. 10: 1318; Par. 63 & 107: “second level interconnects”), wherein the signal connector (1318) is installed on the package assembly (1300); and (As seen in Fig. 10) the quantum device according to claim 1 (Fig. 3: 130; Fig. 10: 1320; Par. 107), wherein the quantum device (Fig. 3: 158; Fig. 10: 1320) is provided in the package assembly (Fig. 10: 1300), and (As seen in Fig. 10) the lead-out signal line (Fig. 3: 152) is electrically connected to the signal connector (Fig. 3: 158). (As seen in Fig. 3) Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YANG (CN 215008192 U). Regarding Claim 1, YANG discloses: A quantum device, comprising: a quantum chip (Fig. 1a/3a: 1), wherein a signal transmission element (Fig. 1a: one of 12, 13, or 14) and a connecting segment (Fig. 1a/3b: 15) electrically connected to the signal transmission element (one of 12, 13, or 14) are formed on the quantum chip (1); (As seen in Fig. 1a) a package substrate (Fig. 2/3b: 2), wherein a lead-out segment (Fig. 2/3b: 21) and a lead-out signal line (Fig. 2: 22) configured to be electrically connected to a signal connector (Fig. 2: 23) are formed on the package substrate (2), and the lead-out signal line (22) is electrically connected to the lead-out segment (21); and (As seen in Fig. 2) a ball grid array (Fig. 3b: 3) configured to electrically connect the connecting segment (15) to the lead-out segment (21) corresponding to each other. (As seen in Fig. 3b) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROBERTS in view of McRAE “Thin film metrology and microwave loss characterization of indium and aluminum/indium superconducting planar resonators”, 2018. Regarding Claim 8, ROBERTS does not disclose: The quantum device according to claim 7, wherein the superconducting element (SCE) is made of indium. However, ROBERTS does disclose in Par. 50 that the claimed superconducting element may be made of any of a number of listed superconducting materials, e.g. aluminum, niobium, etc. And ROBERTS further discloses “other suitable superconductors and alloys of superconductors may be used as well”. But ROBERTS fails to explicitly disclose indium as a possible superconducting material for the superconducting element. McRAE discloses: the superconducting element is made of indium. (See Abstract & Results, regarding thermally evaporated “TE” indium without annealing or HF treatments.) Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of ROBERTS with those of McRAE such that the superconducting element—and other portions of the claimed signal transmission element—of ROBERTS is made of thermally evaporated indium, as taught by McRAE, as both ROBERTS and McRAE regard qubit devices and the superconducting interconnections therein. Further, the superconducting interconnect materials of both ROBERTS and McRAE are recognized in the art for the same purpose of carrying/transmitting/driving/etc. microwave resonance signals for the associated qubit (ROBERTS Par. 41 – 51; McRAE Abstract/Introduction), MPEP 2144.06. Further still, McRAE teaches thermally evaporated indium functions particularly well for this purpose, showing low two-level state losses compared to other materials studied, (McRAE Fig. 4). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST).. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Oct 17, 2023
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
80%
With Interview (+8.3%)
3y 7m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allowance rate.

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