DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of Chang et al. (U.S. Patent No. 11,094,701 B2), hereafter “Chang ‘701”. Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasons below.
Claims of Chang ‘701
Claims of the Instant Application
(Claim 1): A layout structure of a storage cell, comprising: a transistor, formed in a semiconductor substrate; a plurality of fuses, formed in at least one conductive layer on the semiconductor substrate, for coupling a connecting terminal of the transistor; a bit line, arranged to couple the plurality of fuses; and a word line, arranged to couple a control terminal of the transistor.
Although Chang ‘701 does not explicitly teach forming a transistor on a semiconductor substrate, forming a transistor in a semiconductor substrate necessarily forms it on the semiconductor substrate.
Although Chang ‘701 does not explicitly teach a first fuse and a second fuse, “a plurality of fuses” at minimum includes a first fuse and a second fuse.
Although Chang ‘701 does not explicitly teach a first conductive layer, “at least one conductive layer” at minimum includes a first conductive layer.
Although Chang ‘701 does not explicitly teach a gate, the Examiner takes Official Notice that “a control terminal of a transistor” is understood in the art as a gate structure.
(Claim 16): A method of forming a storage cell, comprising: forming a transistor on a semiconductor substrate; forming a first fuse and a second fuse in a first conductive layer over the semiconductor substrate; forming a bit line to couple to the first fuse and the second fuse; and forming a word line to couple to a gate of the transistor.
Claim Rejections 35 U.S.C. § 102(a)(1)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Wang et al. (U.S. Patent Publication No. 2014/0001568 A1), hereafter “Wang”.
As to claim 1, Wang teaches:
Forming a transistor 101 on a semiconductor substrate 104. See Wang, FIG. 1.
Forming a plurality of fuses 102/136 in at least one conductive layer (the at least one conductive layer comprising 134 or 134/304 in FIG. 3) on the semiconductor substrate to couple a connecting terminal 108 of the transistor. Wang teaches a plurality of fuses in FIG. 8 and each one of them is formed like FIG. 1 or FIG. 3. Id. at FIG. 1, FIG. 3, FIG. 8.
Forming a bit line (128/“Bit Line”) to couple the plurality of fuses. Id. at FIG. 1, FIG. 8.
Forming a word line (129/”Word Line”) to couple a control terminal 110 of the transistor.
As to claim 2, Wang teaches the plurality of fuses are connected in series between the bit line and the connecting terminal of the transistor. Id. at FIG. 8.
As to claim 3, Wang teaches forming a first fuse 136/832 having a first conductive pad 114 coupled to the connecting terminal 108 of the transistor; and forming a second fuse 136/842 having a first conductive pad 114 coupled to a second conductive pad of the first fuse, wherein a second conductive pad of the second fuse is coupled to the bit line. Id.
As to claim 5, Wang teaches the first and second fuse 832, 842 formed similarly such that they are disposed in a same conductive layer (134 or 134/304) on the semiconductor substrate.
Claims Allowable If Rewritten in Independent Form
Claims 4, 6, 7, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 4, Wang does not teach a second conductive layer different from the irst conductive layer.
As to claim 6, Wang does not teach a third fuse.
As to claims 17, 18, and 20, Chang ‘701 does not teach the claimed limitations.
Indication of Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: claims 8-15 are indicated as being allowable.
As to claim 8, Chang et al. (U.S. Patent Publication No. 2017/0345827 A1), hereafter Chang, teaches forming a transistor 106/107 on a semiconductor substrate; forming a first fuse (103 or 105) in a first conductive layer M0 over the semiconductor substrate; forming a second fuse (102 or 104) in a second conductive layer M2 over the first conductive layer (the Examiner notes the second fuse is not required to be formed directly over the first conductive layer); forming a word line (paragraph [0019]) to couple to a gate of the transistor. See Chang, FIG. 1A, FIG. 1B.
However, Chang does not teach “forming a bit line to couple to the first fuse and the second fuse”. Although Chang teaches multiple bit lines BL0-BL3, the Examiner notes that claim 8 specifies a singular bit line coupling to two fuses. The parallel layout of Chang FIG. 1A instead depicts a single bit line coupled to a single fuse, e.g. each fuse of 102-105, so that two bit lines are couples to two fuses.
Prior Art Not Relied Upon
The following prior art was not relied upon but is made of record:
Liaw (U.S. Patent Publication No. 2020/0135746 A1)
Conclusion
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/SUBERR L CHI/Primary Examiner, Art Unit 2893
