DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicants’ arguments filed on 07/27/2026 have been fully considered but they are not persuasive for at least the following reasons:
Regarding claim 1:
Applicant arguments: Applicants respectfully submit that the combination of Felsl and Sugawara fails to disclose “when the parasitic transistor is turned on, the control unit controls, to 0.9 ps or less, a turn-off time of the corresponding MOSFET”. The Examiner disagrees.
In response:
Felsl discloses in Para [ 0060] discloses “circuit diagrams of the IGBT 100 and 200. Both IGBTs include a MOSFET M.sub.1 and M.sub.2, respectively, a collector-side transistor T.sub.1 and T.sub.2, respectively, and a parasitic transistor T.sub.p1 and T.sub.p2, respectively.”); and
a control unit (circuitry, e.g. for a given inductive load, Para [ 0042]) which controls switching of the MOSFET in each of the plurality of SiC chips (Para [ 0042]).
Sugawara discloses a combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer (Abstract). Sugawara further discloses “(Para [ 0180-0181] discloses “The turn-on time and the turn-off time of the combined switching device according to the third embodiment are 205 ns and 350 ns”.
Therefore, the combination of Felsl and Sugawara disclose discloses above limitation.
Thus, the well-made rejection included in the 05/07/2026 Non-Final Office Action is proper and hereby made FINAL.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara).
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Regarding claim 1. Felsl discloses a semiconductor module comprising:
a plurality of SiC chips (Fig [1-2], IGBT 100 and 200, Para [ 0030-0031]) electrically connected in parallel (Para [ 0037]) and each having a MOSFET and a parasitic transistor that are formed therein (Para [ 0060] discloses “circuit diagrams of the IGBT 100 and 200. Both IGBTs include a MOSFET M.sub.1 and M.sub.2, respectively, a collector-side transistor T.sub.1 and T.sub.2, respectively, and a parasitic transistor T.sub.p1 and T.sub.p2, respectively.”); and
a control unit (circuitry, e.g. for a given inductive load, Para [ 0042]) which controls switching of the MOSFET in each of the plurality of SiC chips (Para [ 0042]), wherein for all of the plurality of SiC chips, when the parasitic transistor is turned on, the control unit controls (Para [ 0042]).
But Felsl does not disclose explicitly controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET.
In a similar field of endeavor, Sugawara discloses controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [ 0180-0181] discloses “The turn-on time and the turn-off time of the combined switching device according to the third embodiment are 205 ns and 350 ns).
Since Felsl and Sugawara are both from the similar field of endeavor, and Sugawara discloses switching time when the MOSFET switch is changed from a turn-on state to a turn-off state. Therefore, the purpose disclosed by Sugawara would have been recognized in the pertinent art of Felsl. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl in light of Sugawara teaching “controls to 0.9 μs or less, a turn-off time of the MOSFET corresponding (Para [ 0180-0181] discloses “The turn-on time and the turn-off time of the combined switching device according to the third embodiment are 205 ns and 350 ns)” for further advantage such as high-speed operation of the combined switching device can be realized.
Regarding claim 3. Felsl and Sugawara discloses the semiconductor module according to claim 1, Felsl further disclose wherein when the parasitic transistor is turned off, the control unit (Para [ 0042]).
But Felsl does not disclose explicitly controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET.
In a similar field of endeavor, Sugawara discloses controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [ 0180-0181]).
Since Felsl and Sugawara are both from the similar field of endeavor, and Sugawara discloses switching time when the MOSFET switch is changed from a turn-on state to a turn-off state. Therefore, the purpose disclosed by Sugawara would have been recognized in the pertinent art of Felsl. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl in light of Sugawara teaching “controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [ 0180-0181])” for further advantage such as high-speed operation of the combined switching device can be realized.
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara) as applied claims above and further in view of FUJIMOTO et al (US 2019/0198620 A1; hereafter FUJIMOTO).
Regarding claim 2. Felsl and Sugawara discloses the semiconductor module according to claim 1, Felsl further discloses wherein the parasitic transistor of each of the plurality of SiC chips is not turned on in a region (Para [ 0042]).
But Felsl and Sugawara does not disclose explicitly where a current density of a main current flowing through the corresponding MOSFET is 6000 A/cm2 or less.
In a similar field of endeavor, FUJIMOTO discloses where a current density of a main current flowing through the corresponding MOSFET is 6000 A/cm2 or less (Abstract).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl and Sugawara in light of FUJIMOTO teaching “where a current density of a main current flowing through the corresponding MOSFET is 6000 A/cm2 or less (Abstract)” for further advantage such as having low ON voltage, high-speed characteristics.
Regarding claim 19. Felsl and Sugawara in light of FUJIMOTO discloses the semiconductor module according to claim 2, Felsl further disclose wherein when the parasitic transistor is turned off, the control unit (Para [ 0042]).
But Felsl does not disclose explicitly controls, to 0.9 μs or less, the turn-off time of the corresponding MOSFET.
In a similar field of endeavor, Sugawara discloses controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [ 0180-0181]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl and FUJIMOTO in light of Sugawara teaching “controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [ 0180-0181])” for further advantage such as high-speed operation of the combined switching device can be realized.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara) as applied claims above and further in view of CHOI et al (US 2014/0175901 A1; hereafter CHOI).
Regarding claim 4. Felsl and Sugawara discloses the semiconductor module according to claim 1, Felsl further discloses wherein when the parasitic transistor is turned off, the control unit controls (Para [ 0042]).
But Felsl and Sugawara does not disclose explicitly control unit controls to a value larger than 0.9 μs, the turn-off time of the corresponding MOSFET.
In a similar field of endeavor, CHOI discloses control unit controls to a value larger than 0.9 μs, the turn-off time of the corresponding MOSFET (Para [0046]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl and Sugawara in light of CHOI teaching “control unit controls to a value larger than 0.9 μs, the turn-off time of the corresponding MOSFET (Para [ 0046])” for further advantage such as improving insertion loss characteristics by varying a resistance value.
Regarding claim 5. Felsl and Sugawara in light of CHOI discloses the semiconductor module according to claim 4, Felsl further discloses wherein the control unit collectively controls the turn-off times of the MOSFETs of all of the plurality of SiC chips (Para [0030-0032, 0042]).
Regarding claim 6. Felsl and Sugawara in light of CHOI disclose the semiconductor module according to claim 4, Felsl further discloses wherein depending on a state of the parasitic transistor of each of the plurality of SiC chips, the control unit individually controls the turn-off time of the corresponding MOSFET (Para [0030-0032, 0042]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara) as applied claims above and further in view of Krug (US 2022/0416766 A1; hereafter Krug).
Regarding claim 7. Felsl and Sugawara in light of CHOI disclose the semiconductor module according to claim 4, But Felsl and Sugawara in light of CHOI does not disclose explicitly further comprising:
a current sensing unit which senses a main current flowing through the MOSFET of at least one of the plurality of SiC chips, wherein the control unit controls the turn-off time of the MOSFET of the at least one of the plurality of SiC chips based on a waveform of the main current sensed by the current sensing unit.
In a similar field of endeavor, Krug discloses a current sensing unit which senses a main current flowing through the MOSFET of at least one of the plurality of SiC chips ( Fig [1,5], current sensing unit 202A ( Para [ 0022-0027]) , wherein the control unit (Controller 106, Para [ 0025-0027]) controls the turn-off time of the MOSFET of the at least one of the plurality of SiC chips based on a waveform of the main current sensed by the current sensing unit (Fig [1,5], Para [ 0022-0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl, Sugawara and CHOI in light of Krug teaching “a current sensing unit which senses a main current flowing through the MOSFET of at least one of the plurality of SiC chips ( Fig [1,5], current sensing unit 202A ( Para [ 0022-0027]) , wherein the control unit (Controller 106, Para [ 0025-0027]) controls the turn-off time of the MOSFET of the at least one of the plurality of SiC chips based on a waveform of the main current sensed by the current sensing unit (Fig [1,5], Para [ 0022-0026])” for further advantage such as determine the voltage drop over the power switch based on a difference between the first signal and the second signal.
Regarding claim 8. Felsl, Sugawara and CHOI in light of Krug discloses the semiconductor module according to claim 7, Krug discloses wherein the control unit controls the turn-off time of the MOSFET (Fig [1,5], Para [ 0022-0026]) of the at least one of the plurality of SiC chips based on a slope of a rising edge of the waveform of the main current sensed by the current sensing unit (Fig [1,5], Para [ 0022-0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl, Sugawara and CHOI in light of Krug teaching “wherein the control unit controls the turn-off time of the MOSFET (Fig [1,5], Para [ 0022-0026]) of the at least one of the plurality of SiC chips based on a slope of a rising edge of the waveform of the main current sensed by the current sensing unit (Fig [1,5], Para [ 0022-0026])” for further advantage such as determine the voltage drop over the power switch based on a difference between the first signal and the second signal.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara) as applied claims above and further in view of TANIOKA et al (US 2017/0250254 A1; hereafter TANIOKA).
Regarding claim 9. Felsl and Sugawara discloses the semiconductor module according to claim 1, Felsl further discloses MOSFET of each of the plurality of SiC chips (Para [ 0030-0031, 0060-0061]).
But Felsl and Sugawara does not disclose explicitly wherein an acceptor concentration of a base region of the MOSFET is 1×1017/cm3 or more.
In a similar field of endeavor, TANIOKA discloses wherein an acceptor concentration of a base region of the MOSFET is 1×1017/cm3 or more (Para [ 0070, 0078]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl and Sugawara in light of TANIOKA teaching “wherein an acceptor concentration of a base region of the MOSFET is 1×1017/cm3 or more (Para [ 0070, 0078])” for further advantage such as to control resistance in the channel region to improve device performance.
Regarding claim 10. Felsl and Sugawara in light of TANIOKA discloses the semiconductor module according to claim 9, Felsl further discloses MOSFET of each of the plurality of SiC chips (Para [ 0030-0031, 0060-0061]).
But Felsl and Sugawara does not disclose explicitly wherein the acceptor concentration of the base region of the MOSFET is 8×1017/cm3 or more.
In a similar field of endeavor, TANIOKA discloses wherein the acceptor concentration of the base region of the MOSFET is 8×1017/cm3 or more (Para [ 0070, 0078]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl and Sugawara in light of TANIOKA teaching “wherein the acceptor concentration of the base region of the MOSFET is 8×1017/cm3 or more” for further advantage such as to control resistance in the channel region to improve device performance.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara) as applied claims above and further in view of Sandow et al (US 2022/0102478 A1; hereafter Sandow).
Regarding claim 11. Felsl and Sugawara discloses semiconductor module according to claim 1, But Felsl and Sugawara does not disclose explicitly wherein a maximum value of a contact resistance of a contact region of the MOSFET of each of the plurality of SiC chips is 9.0 or less.
In a similar field of endeavor, Sandow discloses wherein a maximum value of a contact resistance of a contact region of the MOSFET of each of the plurality of SiC chips is 9.0 or less (Para [ 0142]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl and Sugawara in light of Sandow teaching “wherein a maximum value of a contact resistance of a contact region of the MOSFET of each of the plurality of SiC chips is 9.0 or less (Para [ 0142])” for further advantage such as to control resistance to improve device performance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of Sugawara (US 2013/0001703 A1; hereafter Sugawara) and FUJIMOTO et al (US 2019/0198620 A1; hereafter FUJIMOTO) as applied claims above and further in view of CHOI et al (US 2014/0175901 A1; hereafter CHOI).
Regarding claim 20. Felsl and Sugawara in light of FUJIMOTO discloses semiconductor module according to claim 2, Felsl further disclose wherein when the parasitic transistor is turned off, the control unit (Para [ 0042]).
But Felsl and Sugawara in light of FUJIMOTO does not disclose explicitly control unit controls to a value larger than 0.9 μs, the turn-off time of the corresponding MOSFET.
In a similar field of endeavor, CHOI discloses control unit controls to a value larger than 0.9 μs, the turn-off time of the corresponding MOSFET (Para [0046]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl, Sugawara and FUJIMOTO in light of CHOI teaching “control unit controls to a value larger than 0.9 μs, the turn-off time of the corresponding MOSFET (Para [ 0046])” for further advantage such as improving insertion loss characteristics by varying a resistance value of a gate resistor of a metal oxide semiconductor (MOS) transistor.
ALTERNATE REJECTION:
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Felsl et al (US 2012/0098097 A1; hereafter Felsl) in view of IKEDA (US 2022/0224327 A1; hereafter IKEDA).
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Regarding claim 1. Felsl discloses a semiconductor module comprising:
a plurality of SiC chips (Fig [1-2], IGBT 100 and 200, Para [ 0030-0031]) electrically connected in parallel (Para [ 0037]) and each having a MOSFET and a parasitic transistor that are formed therein (Para [ 0060] discloses “circuit diagrams of the IGBT 100 and 200. Both IGBTs include a MOSFET M.sub.1 and M.sub.2, respectively, a collector-side transistor T.sub.1 and T.sub.2, respectively, and a parasitic transistor T.sub.p1 and T.sub.p2, respectively.”); and
a control unit (circuitry, e.g. for a given inductive load, Para [ 0042]) which controls switching of the MOSFET in each of the plurality of SiC chips (Para [ 0042]), wherein for all of the plurality of SiC chips, when the parasitic transistor is turned on, the control unit controls (Para [ 0042]).
But Felsl does not disclose explicitly controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET.
In a similar field of endeavor, IKEDA discloses controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [0032-0036]).
Since Felsl and IKEDA are both from the similar field of endeavor, and Sugawara discloses switching time when the MOSFET switch is changed from a turn-on state to a turn-off state. Therefore, the purpose disclosed by IKEDA would have been recognized in the pertinent art of Felsl. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Felsl in light of IKEDA teaching “controls to 0.9 μs or less, a turn-off time of the corresponding MOSFET (Para [0032-0036])” for further advantage such as high-speed operation of the combined switching device can be realized. In addition, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. In re Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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