CTNF 18/489,056 CTNF 100948 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Inve ntion I—Claims 1 – 10—and Species II—as presented in at least Fig. 15— in the reply filed on 16 March 2026 is acknowledged. 08-06 AIA Claim s 11 – 13 & 15 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 16 March 2026 . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Regarding Claim 8 , “a width of the first set of nanosheets is narrower than a width of the second set of nanosheets” is not shown. Therefore, these claimed features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The drawings are further objected to because no part numbers are given in the drawings for the first through eighth FETs claimed. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not indicative of the invention to which the claims are directed. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: STACKED FET WITH SYMMETRIC CELL BOUNDARY COMPRISING GATE CUT REGION WITH CONDUCTIVE VIA . Claim Objections Claims 2 & 9 are objected to because of the following informalities. Claim 2 recites in full, “The semiconductor structure of claim 1, wherein the cell unit is a first cell unit, further comprising a second cell unit, the second cell unit comprising: a third FET stacked on top of a fourth FET; and a third cell boundary made of the second gate cut region with the second width; and a fourth cell boundary made of a third gate cut region with a third width, wherein the third width of the third gate cut region is substantially same as the first width of the first gate cut region and is narrower than the second width of the second gate cut region, and wherein the first cell unit and the second cell unit has a same cell height.” However, the grammatical structure makes the meaning of this claim unclear. For clarity of record, the Examiner suggests the following language, “The semiconductor structure of claim 1, wherein the cell unit is a first cell unit , further comprising a second cell unit, the second cell unit comprising: a third FET stacked on top of a fourth FET; and a third cell boundary made of the second gate cut region with the second width; and a fourth cell boundary made of a third gate cut region with a third width, wherein the third width of the third gate cut region is substantially same as the first width of the first gate cut region and is narrower than the second width of the second gate cut region, and wherein the cell unit is a first cell unit, and wherein the first cell unit and the second cell unit has a same cell height.” Claim 9 recites in full, “The semiconductor structure of claim 1, wherein the cell unit is a first cell unit, further comprising a second cell unit, the second cell unit comprising: a third FET stacked on top of a fourth FET; and a third cell boundary made of a third gate cut region with a third width; and a fourth cell boundary made of the first gate cut region with the first width, wherein the third width of the third gate cut region is substantially same as the first width of the first gate cut region, and wherein the first cell unit has a cell height that is smaller than a cell height of the second cell unit.” However, the grammatical structure makes the meaning of this claim unclear. For clarity of record, the Examiner suggests the following language, “The semiconductor structure of claim 1, wherein the cell unit is a first cell unit, further comprising a second cell unit, the second cell unit comprising: a third FET stacked on top of a fourth FET; and a third cell boundary made of a third gate cut region with a third width; and a fourth cell boundary made of the first gate cut region with the first width, wherein the third width of the third gate cut region is substantially same as the first width of the first gate cut region, and wherein the cell unit is a first cell unit, and wherein the first cell unit has a cell height that is smaller than a cell height of the second cell unit.” Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-02-aia Claim 1 is rejected under 35 U.S.C. 102(a)(2) as anticipated by XIE (US 20240072047 A1). The applied reference has a common Applicant and common joint inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. EXAMINER’S NOTE For Fig. 4C of XIE, consider both the figure from the original reference as well as the annotated figure of the same provided below. PNG media_image1.png 385 410 media_image1.png Greyscale Regarding Claim 1 , XIE discloses : A semiconductor structure (Fig. 4C) comprising a cell unit (Fig. 4C: from the right half of the left 48 to the left half of 49; hereinafter CELL) , the cell unit (CELL) comprising: a first field-effect-transistor (FET) (Fig. 4C: FET associated with 42 of CELL) stacked on top of a second FET (Fig. 4C: FET associated with 38 of CELL) ; a first cell boundary made of a first gate cut region (Fig. 4C: left 48) with a first width (Fig. 4C: width of 48 in the horizontal direction; hereinafter W1) ; and a second cell boundary made of a second gate cut region (Fig. 4C: 49) with a second width (Fig. 4C: width of 49 in the horizontal direction; hereinafter W2) , wherein the second width ( W2 ) of the second gate cut region (49) is wider than the first width ( W1 ) of the first gate cut region (left 48) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim(s) 1 – 10 & 14 is/are reject ed under 35 U.S.C. 103 as being unpatentable over KIM (US 20240365527 A1) i n view of HUANG (US 20230307285 A1). EXAMINER’S NOTE For Fig. 2 A, 2B, & 3B of KIM, consider both the figures from the original reference as well as the annotated figures of the same provided below, where element “LOR” regards a line of reflection. For evidence said reflection is accurate, particularly for Fig. 3B, see Par. 88 – 89 of KIM. PNG media_image2.png 749 553 media_image2.png Greyscale PNG media_image3.png 757 506 media_image3.png Greyscale PNG media_image4.png 660 909 media_image4.png Greyscale Regarding Claim 1 , KIM discloses : A semiconductor structure ( Fig. 2A – 3D ) comprising a cell unit ( Fig. 2A/2B/3B: CELL1 ), the cell unit ( CELL1 ) comprising: a first field-effect-transistor (FET) ( Fig. 2A: upper left UAR2/UGE; Fig. 3B: FET associated with USD2 left of LOR; hereinafter FET1 ) stacked on top of a second FET (Fig. 2B: upper right LAR2/LGE; Fig. 3B: FET associated with LSD2 left of LOR; hereinafter FET2) ; a first cell boundary made of a first gate cut region (Fig. 2A: left half of first LCT above LOR; Fig. 2B: right half of first LCT above LOR; Fig. 3B: LCT1) with a first width (Fig. 3B: W1) ; and a second cell boundary made of a second gate cut region (Fig. 2A: left half of LCT split by LOR; Fig. 2B: right half of LCT split by LOR; Fig. 3B: LCT2) with a second width (Fig. 3B: W2) KIM does not disclose : wherein the second width ( W2 ) of the second gate cut region (LCT2) is wider than the first width ( W1 ) of the first gate cut region (LCT1) . HUANG discloses : a second gate cut region (Fig. 1A/1G: 108/106) with a second width (Fig. 1G: T2) and a conductive via (108) formed inside the second gate cut region (108/106) Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of KIM with those of HUANG to enable the device of KIM to comprise a conductive via formed inside the second gate cut region—as well as to enable the device of KIM to comprise the associated contact structures electrically connecting said conductive via and associated source/drain regions, as disclosed by HUANG (HUANG Fig. 1G) —as doing so yields a reduction in the total device area occupied by the conductive via and gate cut region compared to when these components are formed adjacent to one another, HUANG Par. 17. Further still, as a direct consequence of forming the conductive via within the second gate cut region, the second width of the second gate cut region is widened, as seen in HUANG Fig. 1A & 1H, thereby satisfying the limitation: wherein the second width of the second gate cut region is wider than the first width of the first gate cut region. Regarding Claim 2 , KIM discloses : The semiconductor structure of claim 1, wherein the cell unit (CELL1) is a first cell unit (CELL1) , further comprising a second cell unit (Fig. 2A/2B/3B: CELL2) , the second cell unit (CELL2) comprising: a third FET (Fig. 2A: lower left UAR2/UGE; Fig. 3B: FET associated with USD2 right of LOR; hereinafter FET3) stacked on top of a fourth FET (Fig. 2B: lower right LAR2/LGE; Fig. 3B: FET associated with LSD2 right of LOR; hereinafter FET4) ; and a third cell boundary made of the second gate cut region (LCT2) with the second width ( W2 ); and a fourth cell boundary made of a third gate cut region (Fig. 2A: left half of first LCT below LOR; Fig. 2B: right half of first LCT below LOR; Fig. 3B: LCT3) with a third width (Fig. 3B: W3) , wherein the third width (W3) of the third gate cut region (LCT3) is substantially same as the first width (W1) of the first gate cut region (LCT1) …and wherein the first cell unit (CELL1) and the second cell unit (CELL2) has a same cell height (Fig. 3B: distance in the D1 direction between vertical LCT center lines) . KIM does not disclose : the third width (W3) of the third gate cut region (LCT3) …is narrower than the second width (W2) of the second gate cut region (LCT2) KIM in view of HUANG discloses : the third width of the third gate cut region…is narrower than the second width of the second gate cut region The combination of KIM in view of HUANG, as provided in Claim 1, satisfies this limitation, as Claim 2 requires—and KIM discloses—the first width and the third width to be substantially the same, and said combination yields the first width narrower than the second width. Therefore, KIM in view of HUANG satisfies the limitation: the third width of the third gate cut region is narrower than the second width of the second gate cut region. Further, note the symmetry in the device of HUANG about the second gate cut region (HUANG Fig. 1A/1G: 108/106) also suggests this combination will maintain the first cell unit and the second cell unit having a same cell height. Regarding Claim 3 , KIM discloses : The semiconductor structure of claim 2, wherein a source/drain (S/D) region (Fig. 3B: USD2 left of LOR) of the first FET (FET1) and a S/D region (Fig. 3B: USD2 right of LOR) of the third FET (FET3) are mirror-symmetry with respect to the second gate cut region (LCT2) , and a S/D region (Fig. 3B: LSD2 left of LOR) of the second FET (FET2) and a S/D region (Fig. 3B: LSD2 right of LOR) of the fourth FET (FET4) are mirror-symmetry with respect to the second gate cut region (LCT2) . Regarding Claim 4 , KIM does not disclose : The semiconductor structure of claim 2, further comprising a conductive via formed inside the second gate cut region, wherein a source/drain (S/D) region of the first FET is conductively connected to a backside power rail by the conductive via, and the second gate cut region insulates the conductive via from the second FET and the fourth FET. HUANG discloses : a conductive via (Fig. 1A/1G: 108) formed inside the second gate cut region (Fig. 1A/1G: 108/106) , wherein a source/drain (S/D) region (Fig. 1G: 120B2-2) of the first FET (Fig. 15B: top half of 102B, which is 102B2; Par. 60; See also Fig. 1G: 102B2) is conductively connected to a backside power rail (Par. 16 & 38) by the conductive via (108) , and the second gate cut region (108/106) insulates the conductive via (108) from the second FET (Fig. 15B: bottom half of 102B, which is 102B1; Par. 60; See also Fig. 1G: 102B1) and the fourth FET (Fig. 1B/1G: 102A1) . As seen in Fig. 1A – 1H, 106 of 108/106 insulates 108 from all parts of 102A1. While 106 does not similarly insulate 108 from all parts of 102B1—e.g. 108 is electrically connected to 120B1-2 of 102B1 in Fig. 1G—106 does insulate 108 from all other parts of 102B1. That is, 108/106 partially insulates 108 from 102B1. Therefore, by a broad but reasonable interpretation, 108/106 insulates 108 from 102B1, satisfying the limitations of this claim. Regarding Claim 5 , KIM does not disclose : The semiconductor structure of claim 2, further comprising a conductive via formed inside the second gate cut region, wherein a source/drain (S/D) region of the third FET is conductively connected to a middle-of-line contact at a front side of the semiconductor structure, and the second gate cut region insulates the conductive via from the first FET and the third FET. HUANG discloses : a conductive via ( Fig. 1A/1G: 108 ) formed inside the second gate cut region ( Fig. 1A/1G: 108/106 ), wherein a source/drain (S/D) region (Fig. 1G: 120A2-2) of the third FET (Fig. 1B/1G: 102A2) is conductively connected to a middle-of-line contact at a front side of the semiconductor structure (Par. 38) , and the second gate cut region (108/106) insulates the conductive via (108) from the first FET (102B2, as described in Claim 4) and the third FET (As seen in Fig. 1A – 1H, 108/106 insulates 108 from 102A2) . By reasoning analogous to that used for Claim 4, 108/106 partially insulates 108 from 102B2. Therefore, by a broad but reasonable interpretation, 108/106 insulates 108 from 102B2, satisfying the limitations of this claim. Regarding Claim 6 , KIM discloses : The semiconductor structure of claim 3, wherein the S/D region (Fig. 3B: LSD2 right of LOR) of the fourth FET (FET4) is connected to a middle-of-line contact (Fig. 3B: ND1 right of LOR) through a deep-via (Fig. 3B: LVI right of LOR) . Regarding Claim 7 , KIM discloses : The semiconductor structure of claim 3, wherein the S/D region (Fig. 3B: LSD2 left of LOR) of the second FET (FET2) is connected to a backside power rail (Par. 73; See also Fig. 1) through a backside contact ( Fig. 3B: ND1 left of LOR ). Regarding Claim 8 , KIM discloses : The semiconductor structure of claim 2, wherein the first FET (FET1) and the second FET (FET2) are a first and a second nanosheet transistor having a first set of nanosheets ( Corresponding to Fig. 3A: SP3/SP4 of UAR1 ) and a second set of nanosheets (Corresponding to Fig. 3A: SP1/SP2 of LAR1) respectively, and wherein a width (Corresponding to Fig. 3A: the width in the D3 direction of SP3) of the first set of nanosheets is narrower than a width (Corresponding to Fig. 3A: the width in the D2 direction of SP1) of the second set of nanosheets. (Consult Par. 38 & 39 for evidence of the correspondence between the nanosheets of UAR1 and UAR2—and thus FET1—as well as that of LAR1 and LAR2—and thus FET2.) Regarding Claim 9 , KIM discloses : The semiconductor structure of claim 1, wherein the cell unit (CELL1) is a first cell unit (CELL1) , further comprising a second cell unit (Fig. 2A/2B/3B: CELL22) , the second cell unit (CELL22) comprising: a third FET (Fig. 2A: upper left UAR1/UGE) stacked on top of a fourth FET (Fig. 2B: upper right LAR1/LGE) ; and a third cell boundary made of a third gate cut region (Fig. 2A: left half of top LCT; Fig. 2B: right half of top LCT; Fig. 3B: LCT33) with a third width (Fig. 3B: width of LCT33 in a diagonal direction in the D1-D3 plane such that the resulting width—hereinafter W33—is substantially the same as W1) ; and a fourth cell boundary made of the first gate cut region (LCT1) with the first width ( W1 ), wherein the third width (W33) of the third gate cut region (LCT33) is substantially same as the first width (W1) of the first gate cut region (LCT1) , and wherein the first cell unit (CELL1) has a cell height (Fig. 3B: the distance in the D1 direction between LCT centerlines of CELL1) that is smaller than a cell height (Fig. 3B: the height in the D3 direction of LCT33) of the second cell unit (CELL22) . Regarding Claim 10 , KIM discloses : The semiconductor structure of claim 2, further comprising a third cell unit (Fig. 2A/2B/3B: CELL3) , the third cell unit (CELL3) comprising: a fifth FET (Fig. 2A: lower left UAR1/UGE; hereinafter FET5) stacked on top of a sixth FET (Fig. 2B: lower right LAR1/LGE; hereinafter FET6) ; and a fifth cell boundary made of the third gate cut region (LCT3) with the third width (W3) ; and a sixth cell boundary made of a fourth gate cut region (Fig. 2A/2B: both left and right halves of bottom LCT; Fig. 3B: LCT4) with a fourth width (Fig. 3B: width of LCT4 in a diagonal direction in the D1-D3 plane such that the resulting width—hereinafter W4—is substantially the same as the second width of the second gate cut region of the combination of KIM view of HUANG, as presented for Claim 1) , wherein the fourth width (W4) of the fourth gate cut region (LCT4) …is wider than the third width (W3) of the third gate cut region (LCT3) , and (As stated for Claims 1 & 2, KIM alone discloses W1, W2, and W3 are substantially the same. Further, the combination of KIM in view of HUANG yields the second width—which is substantially the same as the fourth width W4 for KIM alone, by definition—being wider than the second width W2 of KIM alone. Therefore, KIM alone discloses W4 of LCT4 is wider than W2 of LCT2 and, thus wider than W3 of LCT3.) wherein the first cell unit (CELL1) , the second cell unit (CELL2) , and the third cell unit (CELL3) has a same cell height (Fig. 3B: the height in the D3 direction of a given LCT) . KIM does not disclose : the fourth width (W4) of the fourth gate cut region (LCT4) is substantially same as the second width ( W2 ) of the second gate cut region (LCT2) KIM in view of HUANG discloses : the fourth width of the fourth gate cut region is substantially same as the second width of the second gate cut region The combination of KIM in view of HUANG, as provided in Claim 1, satisfies this limitation, as this combination results in the widening of the second width of the second gate cut region of KIM—as previous stated—and the resulting second width of this combination is defined to be substantially the same as the fourth width of the fourth gate cut region of KIM. Regarding Claim 14 , KIM discloses : The semiconductor structure of claim 10, further comprising a fourth cell unit (Fig. 2A/2B: CELL4) , the fourth cell unit (CELL4) comprising: a seventh FET (Fig. 2A: lower right UAR1/UGE; hereinafter FET7) stacked on top of an eighth FET (Fig. 2B: lower left LAR1/LGE, hereinafter FET8) ; and a seventh cell boundary made of the fourth gate cut region (LCT4) with the fourth width (W4) ; and a eighth cell boundary made of a fifth gate cut region (Fig. 2A: right half of first LCT below LOR; Fig. 2B: left half of first LCT below LOR; hereinafter LCT5) with a fifth width (Fig. 3B: width of the first LCT right of LOR in a diagonal direction in the D1-D3 plane such that the resulting width—hereinafter W5—is substantially the same as W4. For evidence these dimensions apply to CELL4, consult the symmetry disclosed in Par. 88 – 89) wherein the fifth width (W5) of the fifth gate cut region (LCT5) is substantially same as the fourth width (W4) of the fourth gate cut region (LCT4) and is wider than the third width (W3) of the third gate cut region (LCT3) , and (As W5 is substantially the same as W4, and W4 is wider than W3—as indicated for Claim 10—W5 of LCT5 is wider than W3 of LCT3) wherein the third cell unit (CELL3) has a cell height (Fig. 3B: height of a given LCT of CELL3 in the D3 direction) that is larger than a cell height (Fig. 3B: distance in the D1 direction between vertical LCT center lines of CELL3. For evidence the latter applies to CELL4, consult the symmetry disclosed in Par. 88 – 89) of the fourth cell unit (CELL4) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST).. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/489,056 Page 2 Art Unit: 2898 Application/Control Number: 18/489,056 Page 3 Art Unit: 2898 Application/Control Number: 18/489,056 Page 4 Art Unit: 2898 Application/Control Number: 18/489,056 Page 5 Art Unit: 2898 Application/Control Number: 18/489,056 Page 6 Art Unit: 2898 Application/Control Number: 18/489,056 Page 7 Art Unit: 2898 Application/Control Number: 18/489,056 Page 8 Art Unit: 2898 Application/Control Number: 18/489,056 Page 9 Art Unit: 2898 Application/Control Number: 18/489,056 Page 10 Art Unit: 2898 Application/Control Number: 18/489,056 Page 11 Art Unit: 2898 Application/Control Number: 18/489,056 Page 12 Art Unit: 2898 Application/Control Number: 18/489,056 Page 13 Art Unit: 2898 Application/Control Number: 18/489,056 Page 14 Art Unit: 2898 Application/Control Number: 18/489,056 Page 15 Art Unit: 2898 Application/Control Number: 18/489,056 Page 16 Art Unit: 2898 Application/Control Number: 18/489,056 Page 17 Art Unit: 2898
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