DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding Applicant’s amendments to the claims addressing the rejections under 35 U.S.C. 112(b) in the reply filed 24 June 2026, Applicant’s amendments are acknowledged and have overcome the associated previous rejections. Therefore, the associated previous rejections are hereby withdrawn.
Regarding Applicant’s comments directed toward related document U.S. Patent 12,658,915 B2, the Examiner thanks Applicant for being thorough. However, no double patenting concerns appear to be present with respect to this document.
Regarding the finality of the present Office Action, Applicant argues in the reply filed 24 June 2026 that “any subsequent Office Action with a prior art rejection should be non-final.” Applicant’s arguments in this regard have been fully considered but are not found persuasive. The present prior art rejection was necessitated by Applicant’s amendments resolving the previously identified rejections for indefiniteness under 35 U.S.C. 112(b), which permitted the claimed subject matter to be meaningfully searched and evaluated for patentability. Accordingly, finality is deemed proper. See MPEP § 706.07(a).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 & 3 – 4—and their respective dependent claims—are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 1,
Lin. 9 – 10 recite the limitation “the second sub-switch comprises a first GaN FET and a second GaN FET connected in a back-to-back configuration”. However, this phrase does not clearly define the required electrical relationship between the first and second GaN FETs. In particular, the language does not distinguish a series connection from a parallel connection, making the metes and bounds of the claim unclear.
For the purposes of examination this limitation will be interpreted as “the second sub-switch comprises a first GaN FET and a second GaN FET connected in a series configuration”.
Lin. 9 – 10 recite the limitation “the second sub-switch comprises a first GaN FET and a second GaN FET connected in a series configuration having a common gate and a source”. However, this phrase does not clearly define the required electrical relationship between the source and the series configuration. In particular, the language does not distinguish whether the source is shared/common in the required series configuration of the first and second GaN FETs or if the source is not shared/common, making the metes and bounds of the claim unclear.
For the purposes of examination this limitation will be interpreted as “the second sub-switch comprises a first GaN FET and a second GaN FET connected in a series configuration having a common gate and a common source”.
Lin. 11 – 12 recite the limitation “the common gate of the first and second back-to-back GaN FETs of the second sub-switch”. In light of the associated 112(b) rejection above, for the purposes of examination, this limitation will be interpreted as “the common gate of the first and second
Lin. 14 recites the limitation “the source of the second sub-switch”. In light of the associated 112(b) rejection above, for the purposes of examination, this limitation will be interpreted as “the common source of the second sub-switch”.
Regarding Claim 3,
Lin. 3 recites the limitation “the source of the second sub-switch”. In light of the associated 112(b) rejection above, for the purposes of examination, this limitation will be interpreted as “the common source of the second sub-switch”.
Lin. 1 – 5 recite “respective diodes or gate-to-source connected FETs electrically connected between the common source of the second sub-switch and (i) the first power electrode of the three-terminal bidirectional GaN FET switch; and (ii) the second power electrode of the three-terminal bidirectional GaN FET switch,” and this claim appears to treat the following elements recited therein as different elements:
“the first GaN FET and the second GaN FET of the second sub-switch” of Claim1
“the respective diodes or gate-to-source connected FETs” of this claim
However, Fig. 5 & 6 of the elected species appear to disclose that these elements are one and the same. Specifically, when there is established a direct electrical connection between the common source and the common gate (Instant Fig. 5: 190), the required diode structure is formed between the common source and a given power electrode, to include the more visible path from 170-to-160-to-150 (the first GaN FET of the second sub-switch) that shows no apparent connection between the common gate and the common source. Further, by the electrical path P3-to-P4 in Fig. 6 of the elected species, there is no distinction between the more visible path from 170-to-160-to-150 and the more abstract parallel path from 170-to-190-to-150. Similarly, the second GaN FET of the second sub-switch (170-to-160-to-140) appears to be one and the same as the “respective diode or gate-to-source connected FET electrically connected between the common source of the second sub-switch and (i) the first power electrode of the three-terminal bidirectional GaN FET switch”.
Therefore, it is not clear if the claim is referring to these elements as being different or one and the same, making this claim indefinite. For the purposes of examination, this claim language will be interpreted as:
“gate-to-source connections on the first and second GaN FETs of the second sub-switch, wherein the first and second GaN FETs of the second sub-switch are electrically connected between the common source of the second sub-switch and (i) the first power electrode of the three-terminal bidirectional GaN FET switch; and (ii) the second power electrode of the three-terminal bidirectional GaN FET switch.”
Regarding Claim 4,
Lin. 3 recites the limitation “the source of the second sub-switch”. In light of the associated 112(b) rejection above, for the purposes of examination, this limitation will be interpreted as “the common source of the second sub-switch”.
Lin. 3 recites the limitation “the gate of the three-terminal bidirectional GaN FET switch” which lacks a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “the single gate of the three-terminal bidirectional GaN FET switch”.
Lin. 2 – 4 recite “a diode or gate-to-source connected FET electrically connected between the common source of the second sub-switch and the single gate of the three-terminal bidirectional GaN FET switch,” and this claim appears to treat the following elements recited therein as different elements:
“the first GaN FET of the second sub-switch” of Claim1
“a diode or gate-to-source connected FET electrically connected between the common source of the second sub-switch and the single gate of the three-terminal bidirectional GaN FET switch” of this claim
However, Fig. 5 & 6 of the elected species appear to disclose that these elements are one and the same. Specifically, as per the related arguments for the 112(b) rejection of Claim 3, upon which this claim depends, the first GaN FET of the second sub-switch (170-to-160-to-150) appears to be one and the same as the “diode or gate-to-source connected FET electrically connected between the common source of the second sub-switch and the single gate of the three-terminal bidirectional GaN FET switch”. That is, this claim appears to require the already claimed first GaN FET of the second sub-switch comprise a gate-to-source connection (which it does as per 190 and the common connections throughout) and this first GaN FET is connected to the “single gate”, which it is via the 2DEG in Fig. 5 of the elected species.
Therefore, it is not clear if the claim is referring to these elements as being different or one and the same, making this claim indefinite. For the purposes of examination, this claim language will be interpreted as:
“a gate-to-source connection on the first GaN FET of the second sub-switch, wherein the first GaN FET of the second sub-switch is electrically connected between the common source of the second sub-switch and the single gate of the three-terminal bidirectional GaN FET switch.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 8, 10, & 12 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by PRECHTL (US 20170103978 A1).
Regarding Claim 1,
PRECHTL discloses:
A three-terminal bidirectional GaN FET switch (Fig. 4: 70) with a single gate (75/81/89), comprising:
a first sub-switch (71),
a second sub-switch (72/73)
connected in parallel (via 85 and 93) with the first sub-switch (71), and
a field plate (83), wherein:
the first sub-switch (71) comprises
a single gate GaN field effect transistor (FET) (Par. 80) having
first (74) and second (76) power electrodes
which are electrically contiguous (via 85 and 93), respectively, to first (74/80) and second (76/90) power electrodes of the three-terminal bidirectional GaN FET switch (70), and
a gate (75) centrally located between the first (74) and second (76) power electrodes of the first sub-switch (71);
the second sub-switch (72/73) comprises
a first GaN FET (72; Par. 81) and a second GaN FET (73; Par. 82)
connected in a series configuration (via 87 and 92) and having
a common gate (81/89; Par. 81 – 82) and a common source (82/88);
the gate (75) of the first sub-switch (71) is (indirectly) electrically connected (via 86/79/78/77) to the common gate (81/89) of the first (72) and second (73) GaN FETs of the second sub-switch (72/73) to form the single gate (75/81/89) of the three-terminal bidirectional GaN FET switch (70); and
Note, by the disclosed connectivity between 75 and 81/89, 75/81/89 may be construed as a “single gate” under a broadest reasonable interpretation.
the common source (82/88) of the second sub-switch (72/73) is connected to the field plate (83).
Regarding Claim 2,
PRECHTL discloses:
The three-terminal bidirectional GaN FET switch of claim 1, wherein
the three-terminal bidirectional GaN FET switch (70) is formed on a substrate (86/79/78/77), and
the field plate (83) is electrically connected (via 82/87) to the substrate (86/79/78/77).
Regarding Claim 3,
PRECHTL discloses:
The three-terminal bidirectional GaN FET switch of claim 1, further comprising
gate-to-source connections (via 83) on the first (72) and second (73) GaN FETs of the second sub-switch (72/73), wherein the first (72) and second (73) GaN FETs of the second sub-switch (72/73) are electrically connected between the common source (82/88) of the second sub-switch (72/73) and (i) the first (74/80) power electrode of the three-terminal bidirectional GaN FET switch (70); and (ii) the second (76/90) power electrode of the three-terminal bidirectional GaN FET switch (70).
Regarding Claim 4,
PRECHTL discloses:
The three-terminal bidirectional GaN FET switch of claim 3, further comprising
a gate-to-source connection (via 83) on the first (72) GaN FET of the second sub-switch (72/73), wherein the first (72) GaN FET of the second sub-switch (72/73) is electrically connected between the common source (82/88) of the second sub-switch (72/73) and the single gate (75 of 75/81/89 via the 2DEG of 71) of the three-terminal bidirectional GaN FET switch (70).
Regarding Claim 5,
PRECHTL discloses:
The three-terminal bidirectional GaN FET switch of claim 1, wherein
the three-terminal bidirectional GaN FET switch (70) is formed on a substrate (86/79/78/77), and
the gate (75) of the single gate GaN FET of the first sub-switch (71) is (indirectly) electrically connected to the substrate (86/79/78/77).
Regarding Claim 6,
PRECHTL discloses:
The three-terminal bidirectional GaN FET switch of claim 1, wherein
the first sub-switch (71) and the second sub-switch (72/73) are integrated on a single die (Par. 79).
Regarding Claim 7,
PRECHTL discloses:
A three-terminal bidirectional GaN FET switch (Fig. 4: 70) with a single gate (75/81/89), comprising:
first (74/80) and second (76/90) power electrodes,
wherein the single gate (75 of 75/81/89) is centrally located between the first (74 of 74/80) and second (76 of 76/90) power electrodes; and
a field plate (83);
wherein the three-terminal bidirectional GaN FET switch (70) is formed on a substrate (86/79/78/77), and the field plate (83) is electrically connected (via 82) to the substrate (86/79/78/77).
Regarding Claim 8,
PRECHTL discloses:
The three-terminal bidirectional GaN FET switch of claim 7, further comprising
respective diodes or gate-to-source connected FETs (72 and 73) electrically connected (via 87/92) between the substrate (86 of 86/79/78/77) and (i) the first (74/80) power electrode; and (ii) the second (76/90) power electrode.
Regarding Claim 10,
PRECHTL discloses:
A three-terminal bidirectional GaN FET switch (Fig. 4: 70) with a single gate (75/81/89), comprising:
first (74/80) and second (76/90) power electrodes,
wherein the single gate (75 of 75/81/89) is centrally located between the first (74 of 74/80) and second (76 of 76/80) power electrodes; and
a field plate (83); wherein
the three-terminal bidirectional GaN FET switch (70) is formed on a substrate (86/79/78/77),
the single gate (75/81/89) is (indirectly) electrically connected to the substrate (86/79/78/77), and
respective diodes or gate-to-source connected FETs (72 and 73) are electrically connected between the field plate (83) and (i) the first (74/80) power electrode; and (ii) the second (76/90) power electrode.
Regarding Claim 12,
PRECHTL discloses:
A three-terminal bidirectional GaN FET switch (Fig. 4: 70) with a single gate (75/81/89), comprising:
first (74/80) and second (76/90) power electrodes; wherein
the single gate (75 of 75/81/89) is centrally located between the first (74 of 74/80) and second (76 of 76/90) power electrodes; wherein
the three-terminal bidirectional GaN FET switch (70) is formed on a substrate (86/79/78/77); and wherein
respective diodes or gate-to-source connected FETs (72 and 73) are electrically connected (via 87/92) between the substrate (86 of 86/79/78/77) and (i) the first (74/80) power electrode; and (ii) the second (76/90) power electrode.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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