DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Figs. 17 & 18, Claims 1-2, 4, 6 & 7 in the reply filed on 06/22/2026 is acknowledged. Non-elected claims 3, 5 8-10 have been withdrawn as being drawn to on-elected invention.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JAPAN JP2022-167716 filed on 10/19/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/30/2026 and 10/18/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 & 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miura et al. (US 7692454 B2, hereinafter called Miura).
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Regarding claim 1:
Miura discloses in annotated Fig. 8, a semiconductor integrated circuit (semiconductor substrate, Col. 15, lines 30-31) comprising
an input circuit that includes an amplifier (transistors 44, 46), wherein the amplifier includes:
a current source (48) electrically connected to a power supply voltage (Vdd);
a first PMOS transistor (46) having a gate electrically connected to a first node (31) that inputs a data signal, a source (source of transistor 46) electrically connected to the current source (48), and a drain electrically connected to a second node (N2);
a second PMOS transistor (transistor 44) having a gate electrically connected to a third node (32) that inputs a reference signal (e.g. INn may be used as reference signal), a source (source of transistor 44) electrically connected to the current source (48), and a drain electrically connected to a fourth node (N4);
a load circuit (resistors 41 and 42) electrically connected between the second node (N2) and a ground voltage (reference ground where Vss may be ground) and between the fourth node (N4) and the ground voltage (reference ground);
a first NMOS transistor (transistor 56) having a gate electrically connected to the first node, a drain electrically connected to the power supply voltage (Vdd), and a source electrically connected to the fourth node (N4);
a second NMOS transistor (57) having a gate electrically connected to the third node (32), a drain electrically connected to the power supply voltage (Vdd), and a source electrically connected to the second node (N2);
a first current restriction circuit (transistor 58) electrically connected between the drain of the first NMOS transistor (transistor 56) and the power supply voltage (Vdd); and
a second current restriction circuit (transistor 59) electrically connected between the drain of the second NMOS transistor (57) and the power supply voltage (Vdd).
Regarding claim 2:
Miura discloses in annotated Fig. 8, the semiconductor integrated circuit according to claim 1, wherein the load circuit includes:
a first impedance (resistor 42) electrically connected between the second node (N2) and the ground voltage; and
a second impedance (resistor 41) electrically connected between the fourth node (N4) and the ground voltage.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Miura.
Regarding claim 7:
Miura discloses the limitations as applied in claim 1 and further discloses
the gain can be increased through an increase in current, that is, an increase in transistor size (gate width/gate length), Col. 4, lines 50-53) except for the first NMOS transistor and the second NMOS transistor have gate widths smaller than gate widths of the first PMOS transistor and the second PMOS transistor, and the first PMOS transistor and the second PMOS the first PMOS transistor and the second PMOS transistor have gate widths smaller than a gate width of a transistor of the current source. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have selected or chosen the first NMOS transistor and the second NMOS transistor have gate widths smaller than gate widths of the first PMOS transistor and the second PMOS transistor, and the first PMOS transistor and the second PMOS the first PMOS transistor and the second PMOS transistor have gate widths smaller than a gate width of a transistor of the current source, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 4 & 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 is allowable since the closest prior art (i.e. Miura) does not disclose wherein the first current restriction circuit and the second current restriction circuit are PMOS transistors.
Claim 6 is allowable since the closest prior art (i.e. Miura) does not disclose wherein the amplifier includes: a first switch transistor electrically connected between the power supply voltage and the current source; a second switch transistor electrically connected between the power supply voltage and the first NMOS transistor; and a third switch transistor electrically connected between the power supply voltage and the second NMOS transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150016205 A1: KOHNO et al. discloses in Fig. 2, comprising an amplifier circuit includes transistor 100A and transistor 101A wherein gate terminal of the transistor 101A being connected to reference voltage VREF and transistors 101B and 100B and wherein the transistor 101B being connected to the reference voltage VREF.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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