DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species IV, as presented in at least Fig. 10a – 10b, in the reply filed on 17 March 2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: LED CHIP WITH INSULATIVE LAYER STEPS .
Claim Objections
The claims are objected to because they include reference characters which are not enclosed within parentheses.
Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m).
The Examiner further cautions Applicant of minor informalities regarding said reference characters as they appear in the claims, as there appears to be inconsistency in the use of sub-scripts notation, e.g. L1 vs. L1, etc.
The claims are further objected to because of the following informalities:
Regarding Claim 2,
Lin. 1 – 2 cite the limitation “wherein a thickness of the second insulating layer is greater than that of the first insulating layer”. However, the grammatical structure of this limitation renders unclear to what the phrase “that of the first insulating layer” is referring. For the purposes of examination, this limitation will be interpreted as “wherein a thickness of the second insulating layer is greater than a thickness of the first insulating layer”.
Regarding Claim 17,
Lin. 1 – 2 cite the limitation “wherein a thickness of the second insulating layer is greater than that of the first insulating layer”. However, the grammatical structure of this limitation renders unclear to what the phrase “that of the first insulating layer” is referring. For the purposes of examination, this limitation will be interpreted as “wherein a thickness of the second insulating layer is greater than a thickness of the first insulating layer”.
Lin. 4 cites the limitation “a density of the first insulating layer is greater than that of the second insulating layer”. However, the grammatical structure of this limitation renders unclear to what the phrase “that of the second insulating layer” is referring. For the purposes of examination, this limitation will be interpreted as “a density of the first insulating layer is greater than a density
Lin. 5 cites the limitation “a density of the third insulating layer is equal to or less than that of the second insulating layer”. However, the grammatical structure of this limitation renders unclear to what the phrase “that of the second insulating layer” is referring. For the purposes of examination, this limitation will be interpreted as “a density of the third insulating layer is equal to or less than a density
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 10, 16, & 19 – 20—and their respective dependent claims—are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 4,
Lin. 1 – 3 cite the limitation “when the first insulating layer is an atomic layer deposition layer,
a length L1 of the first step beyond the second step is equal to or greater than 100 nm and less than or equal to 5000 nm”, which is a conditional statement of the form “If A is true, then B is true as a consequence” where “A” is the hypothesis, and “B” is the conclusion. However, the hypothesis “when the first insulating layer is an atomic layer deposition layer” is a product-by-process limitation. As such, the only requirement, regarding a prior art rejection, is to provide the first insulating layer, regardless of how the first insulating layer is formed. This drastically alters the hypothesis, and the effect of as much is unclear on the conclusion “a length L1 of the first step beyond the second step is equal to or greater than 100 nm and less than or equal to 5000 nm” rendering this limitation unclear. The Examiner makes no interpretation for the purposes of examination of this limitation.
Lin. 4 – 6 cite the limitation “when the first insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, the length L1 of the first step beyond the second step is equal to or greater than 50 nm and less than or equal to 100 nm”, which is a conditional statement of the form “If A is true, then B is true as a consequence” where “A” is the hypothesis, and “B” is the conclusion. However, the hypothesis “when the first insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer” is a product-by-process limitation. As such, the only requirement, regarding a prior art rejection, is to provide the first insulating layer, regardless of how the first insulating layer is formed. This drastically alters the hypothesis, and the effect of as much is unclear on the conclusion “the length L1 of the first step beyond the second step is equal to or greater than 50 nm and less than or equal to 100 nm” rendering this limitation unclear. The Examiner makes no interpretation for the purposes of examination of this limitation.
Regarding Claim 10,
Lin. 4 cites the limitation “a second insulating layer”. However the antecedent basis is unclear, as this limitation is also cited in Claim 1, upon which this claim depends. For the purposes of examination, this limitation will be interpreted as “the second insulating layer”.
Regarding Claim 16,
Lin. 2 – 3 cite the limitation “an elongation δ of the second structural layer is equal to or less than 50%”. However, the scope of “elongation” is unclear in that “elongation” may take on more than one distinct meaning, e.g. the actual amount by which the second structural layer changes in length due to subsequent processing steps—which would indicate a product-by-process limitation—or the potential amount by which the second structural layer may change under certain stressors—which would indicate a physical property of the second structural layer—or the maximum potential amount by which the second structural layer may change under certain stressors before damage occurs—which would indicated a wholly different physical property of the second structural layer. For the purposes of examination, the Examiner has interpreted the “elongation of the second structure layer” to take on the value of elongation provided in the instant specification for a given material of which the second structure layer may be formed (Instant Specification, Par. 61). However, it should be noted that the instant specification does not define “elongation” but only provides example values for example materials, e.g. “an elongation of titanium (Ti) is 24.94%”.
Regarding Claim 19,
Lin. 2 – 3 cite the limitation “the second insulating layer is disposed to face away from the semiconductor stack layer”. However, the meaning of this limitation is unclear, as a layer does not inherently face in any direction. Although, a given surface of layer does inherently face in the direction normal to said surface, pointing outward from said layer. As such, for the purposes of examination, this limitation will be interpreted as “the second insulating layer is disposed on a surface of the first insulating layer facing
Regarding Claim 20,
Lin. 5 – 6 cite the limitation “the second insulating layer is disposed to face away from the semiconductor stack layer”. However, the meaning of this limitation is unclear, as a layer does not inherently face in any direction. Although, a given surface of layer does inherently face in the direction normal to said surface, pointing outward from said layer. As such, for the purposes of examination, this limitation will be interpreted as “the second insulating layer is disposed on a surface of the first insulating layer facing
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 5, 9, 12 – 14, 16, & 18 – 20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by SEO (US 20200194628 A1).
PNG
media_image1.png
510
944
media_image1.png
Greyscale
PNG
media_image2.png
448
513
media_image2.png
Greyscale
Examiner’s Note
In addition to the original figures of SEO, consider the provided annotated figures of SEO above.
Regarding Claim 1,
SEO discloses:
A light emitting diode (LED) chip (Fig. 1 – 11), comprising
a semiconductor stack layer (110/120) and
an insulating layer (161/162) disposed on the semiconductor stack layer (110/120); wherein the insulating layer (161/162) comprises
a first insulating layer (161) and
a second insulating layer (162) formed on an upper surface of the first insulating layer (161),
the insulating layer (161/162) has a step structure (Fig. 10: As 161 and 162 have multiple horizontal surfaces—and corresponding sidewall surfaces—at various vertical distances from 100, 161/162 as a whole may be considered to have a “step structure” under a broad but reasonable interpretation.), the step structure comprises
a first step (STP1) formed by the first insulating layer (161) and
a second step (STP2) formed by the second insulating layer (162), and
the first step (STP1) extends beyond the second step (STP2) in a horizontal direction (Fig. 10: left-to-right)
(As seen in Fig. 10, the entirety of STP1 extends beyond STP2 in the horizontal direction.)
Regarding Claim 2,
SEO discloses:
The LED chip as claimed in claim 1,
wherein a thickness (THK2) of the second insulating layer (162) is greater than a thickness (THK1) of the first insulating layer (161), and
the thickness (THK2) of the second insulating layer (162) is equal to or greater than 1 micrometer (μm).
(Par. 162: H1 may be 5 µm to 50 µm. As THK2 is clearly greater than H1, THK2 is greater than 1 µm.)
Regarding Claim 3,
SEO discloses:
The LED chip as claimed in claim 1,
wherein in the horizontal direction (Fig. 10: left-to-right), a length L1 of the first step (STP1) beyond the second step (STP2) is equal to or greater than 50 nanometers (nm) and less than or equal to 5000 nm.
(As stated for Claim 1, the entirety of STP1 extends beyond STP2 in the horizontal direction. Further, the length of the entirety of STP1 is clearly greater than the length of H1 in the horizontal direction, which is between 5 µm to 50 µm; Par. 162. Therefore, L1 may be a partial length of the entire length of STP1 such that L1 is equal to or greater than 50 nanometers (nm) and less than or equal to 5000 nm.)
Regarding Claim 5,
SEO discloses:
The LED chip as claimed in claim 1,
wherein a density of the first insulating layer (161, which may be Al2O3, Par. 65) is greater than a density of the second insulating layer (162, which may be SiO2, Par. 94), and
(Of the various densities that are broadly but reasonably associated with 161, one such density is the density of Al2O3 in crystalline form, which is about 4.0 g/cm3. Similarly, of the various densities that are broadly but reasonably associated with 162, one such density is the density of SiO2 in crystalline form, which is about 2.7 g/cm3. Therefore, “a” density of 161 is greater than “a” density of 162.)
a length L1 (As described for L1 in Claim 3) of the first step (STP1) beyond the second step (STP2) is in direct proportion to a difference between the density (4.0 g/cm3 – 2.7 g/cm3 = 1.3 g/cm3) of the first insulating layer (161) and the density of the second insulating layer (162).
(As the proportionality constant is not limited to any range of values, 1.3 may be scaled by any number to yield L1, as described for Claim 3.)
Regarding Claim 9,
SEO discloses:
The LED chip as claimed in claim 1,
wherein the insulating layer (161/162) is provided with a through hole (TH2/TH3) penetrating there through, and
(As seen in Fig. 2)
a sidewall of the through hole (TH2/TH3) forms the step structure; and
(As described in Claim 1, 161/162 as a whole may be considered to have a “step structure” under a broad but reasonable interpretation, part of which is shaped, and thus formed, by the sidewall of TH2/TH3, as this sidewall provides multiple horizontal surfaces—and associated sidewall surfaces—at various vertical distances from 100.)
an end portion of the insulating layer (161/162) is provided with the step structure.
(Fig. 2 shows end portions of 161/162 provided in TH2/TH3 and, thus, with the step structure.)
Regarding Claim 12,
SEO discloses:
The LED chip as claimed in claim 1,
wherein the first insulating layer (161) and the second insulating layer (162) are prepared by the same preparation process (see argument below), and
preparation materials of the first insulating layer (161) and the second insulating (162) layer are different (Par. 65: 161 may be SiO2; Par. 94: 162 may be Si3N4); and
the preparation materials of the first insulating layer (161) and the second insulating layer (162) comprise one or more selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide (Par. 65 & 94).
The language, term, or phrase "the first insulating layer and the second insulating layer are prepared by the same preparation process" is directed towards the process of making “the first insulating layer and the second insulating layer”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product, per se, which must be determined in a "product by process" claim not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the first insulating layer and the second insulating layer are prepared by the same preparation process" only requires “the first insulating layer and the second insulating layer”, which does not distinguish the instant invention from the known invention of SEO, who teaches the structure as claimed.
Regarding Claim 13,
SEO discloses:
The LED chip as claimed in claim 1,
wherein the first insulating layer (161) is made of aluminum oxide (Par. 65).
Regarding Claim 14,
SEO discloses:
The LED chip as claimed in claim 1,
wherein the second insulating layer (162) is a distributed Bragg reflector (DBR) (Par. 94).
Regarding Claim 16,
SEO discloses:
The LED chip as claimed in claim 1,
wherein a second structural layer (150) is formed on a surface (SRF1) of the second insulating layer (162) facing away from the first insulating layer (161); an
(Fig. 10: SRF1 faces away from all portions of 161 to the right of S)
elongation δ of the second structural layer (150) is equal to or less than 50%; and
(Par. 88: 150 may be nickel, which has an elongation of 48.4%, as per the instant specification.)
the second structural layer (150) is made of one of nickel, gold, titanium, chromium, indium tin oxide, titanium oxide, silicon oxide, aluminum oxide, silicon nitride, titanium nitride, or aluminum nitride (Par. 88).
Regarding Claim 18,
SEO discloses:
The LED chip as claimed claim 1,
wherein a first structural layer (100) is formed on a surface of the first insulating layer (161) facing away from the second insulating layer (162), and
(As seen in Fig. 4)
the first structural layer (100) is one of a transparent insulating layer, a transparent conductive layer, or a metal layer.
(Par. 48: 100 may be a sapphire substrate, which is a transparent insulating layer.)
Regarding Claim 19,
SEO discloses:
The LED chip as claimed in claim 1,
wherein the semiconductor stack layer (110/120) is used as a first structural layer (110/120),
the insulating layer (161/162) is disposed on the first structural layer (110/120), and
(As seen in Fig. 2)
the second insulating layer (162) is disposed on a surface of the first insulating layer (161) facing away from the semiconductor stack layer (110/120).
(As seen in Fig. 2)
Regarding Claim 20,
SEO discloses:
The LED chip as claimed in claim 1, further comprising
a substrate (100) acting as a first structural layer (100); wherein
the semiconductor stack layer (110/120) is disposed on the substrate (100) to form a mesa (Fig. 2: 110/120 left of S) structure on the substrate (100),
the insulating layer (161/162) covers at least a sidewall of the semiconductor stack layer (110/120) and a portion (within region S) of the substrate (100) not covered by the semiconductor stack layer (110/120), and
(As seen in Fig. 2)
the second insulating layer (162) is disposed on a surface of the first insulating layer (161) facing away from the semiconductor stack layer (110/120).
(As seen in Fig. 2)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 & 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over SEO in view of DONOFRIO (US 20090283787 A1).
Examiner’s Note
The following references the rejection to Claim 1, as provided above.
Regarding Claim 10,
SEO discloses:
The LED chip as claimed in claim 1, wherein
the first insulating layer (161) is an atomic layer deposition layer (See argument below), and
the second insulating layer (162) is one of an HDPCVD layer, a plasma enhanced chemical vapor deposition (PECVD) layer, or an evaporation deposition layer (See argument below).
The language, term, or phrase "wherein the first insulating layer is an atomic layer deposition layer" is directed towards the process of making “the first insulating layer”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product, per se, which must be determined in a "product by process" claim not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "wherein the first insulating layer is an atomic layer deposition layer" only requires “the first insulating layer”, which does not distinguish the instant invention from the known invention of SEO, who teaches the structure as claimed.
Similarly, the language, term, or phrase "the second insulating layer is one of an HDPCVD layer, a plasma enhanced chemical vapor deposition (PECVD) layer, or an evaporation deposition layer" is directed towards the process of making “the second insulating layer”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product, per se, which must be determined in a "product by process" claim not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the second insulating layer is one of an HDPCVD layer, a plasma enhanced chemical vapor deposition (PECVD) layer, or an evaporation deposition layer" only requires “the second insulating layer”, which does not distinguish the instant invention from the known invention of SEO, who teaches the structure as claimed.
SEO does not disclose:
a thickness of the first insulating layer (161) is in a range from 30 nm to 200 nm
DONOFRIO discloses:
a thickness of the first insulating layer (Fig. 2: 140) is [about 500 nm] (Par. 61).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of SEO with those of DONOFRIO to enable the thickness of the first insulating layer to be about 500 nm in SEO according to the teachings of DONOFRIO, as SEO discloses the first insulating layer but does not disclose an associated thickness. Therefore, a person having ordinary skill in the art would look to the prior art for such a thickness recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the thickness of the first insulating layer of DONOFRIO meets these criteria, as the first insulating layer of SEO and DONOFRIO are similar in that both may comprise similar materials, i.e. dielectrics (SEO, Par. 65; DONOFRIO, Par. 61), and be used for a similar purpose, i.e. to reflect light emitted by the device (SEO, Par. 65; DONOFRIO, Par. 61).
Moreover, DONOFRIO recognizes the thickness of the first insulating layer as a result-effective variable (MPEP 2144.05 II A), as the thickness of the first insulating layer “may be configured to enhance the reflectivity [of the emitted light] based on the operating wavelength of the LED and/or the index of refraction of the insulating layer, using techniques known to those skilled in the art” (DONOFRIO, Par. 61). Furthermore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select a value of the thickness of the first insulating layer in DONOFRIO to fall within the claimed range of 30 nm to 200 nm, achieving the desired effect of enhancing the reflectivity of the emitted light.
Regarding Claim 11,
SEO discloses:
The LED chip as claimed in claim 1,
wherein the first insulating layer (161) is an HDPCVD layer (see argument below), and
the second insulating layer (162) is an evaporation deposition layer (see argument below).
The language, term, or phrase "wherein the first insulating layer is an HDPCVD layer" is directed towards the process of making “the first insulating layer”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product, per se, which must be determined in a "product by process" claim not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "wherein the first insulating layer is an HDPCVD layer" only requires “the first insulating layer”, which does not distinguish the instant invention from the known invention of SEO, who teaches the structure as claimed.
Similarly, the language, term, or phrase "the second insulating layer is an evaporation deposition layer" is directed towards the process of making “the second insulating layer”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product, per se, which must be determined in a "product by process" claim not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the second insulating layer is an evaporation deposition layer" only requires “the second insulating layer”, which does not distinguish the instant invention from the known invention of SEO, who teaches the structure as claimed.
SEO does not disclose:
a thickness of the first insulating (161) layer is in a range from 400 nm to 1000 nm
DONOFRIO discloses:
a thickness of the first insulating layer (Fig. 2: 140) is in a range from 400 nm to 1000 nm (Par. 61: 140 may be 500 nm thick).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of SEO with those of DONOFRIO to enable the thickness of the first insulating layer to be about 500 nm in SEO according to the teachings of DONOFRIO, as SEO discloses the first insulating layer but does not disclose an associated thickness. Therefore, a person having ordinary skill in the art would look to the prior art for such a thickness recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the thickness of the first insulating layer of DONOFRIO meets these criteria, as the first insulating layer of SEO and DONOFRIO are similar in that both may comprise similar materials, i.e. dielectrics (SEO, Par. 65; DONOFRIO, Par. 61), and be used for a similar purpose, i.e. to reflect light emitted by the device (SEO, Par. 65; DONOFRIO, Par. 61).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 & 6 – 8 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by SEO.
Examiner’s Note
In addition to the original figures of SEO, consider the provided annotated figures of SEO above.
Regarding Claim 1,
SEO discloses:
A light emitting diode (LED) chip (Fig. 1 – 11), comprising
a semiconductor stack layer (110/120) and
an insulating layer (161/162) disposed on the semiconductor stack layer (110/120); wherein the insulating layer (161/162) comprises
a first insulating layer (161) and
a second insulating layer (162) formed on an upper surface of the first insulating layer (161),
the insulating layer (161/162) has a step structure (Fig. 10: As 161 and 162 have multiple horizontal surfaces—and corresponding sidewall surfaces—at various vertical distances from 100, 161/162 as a whole may be considered to have a “step structure” under a broad but reasonable interpretation.), the step structure comprises
a first step (STP16) formed by the first insulating layer (161) and
a second step (STP26) formed by the second insulating layer (162), and
the first step (STP16) extends beyond the second step (STP26) in a horizontal direction (Fig. 3: left-to-right).
Regarding Claim 6,
SEO discloses:
The LED chip as claimed claim 1,
wherein an angle α1 (clearly less than 90°) between a side surface (flat portion of SS16) of the first step (STP16) and the horizontal (Fig. 3: left-to-right) direction is smaller than an angle α2 (Approximately 90°) between a side surface (flat portion of SS26) of the second step (STP26) and the horizontal direction (Fig. 3: left-to-right).
Regarding Claim 7,
SEO discloses:
The LED chip as claimed in claim 1,
wherein a side surface (the corner of SS26 where it smoothly transitions into—but before it becomes—the top flat surface of STP26) of the second step (STP26) is a slope surface (Inherently satisfied, as all smooth surfaces have a slope, be it positive, negative, zero, or undefined.), and
(Note, the “transition” region described cannot be an infinitely sharp corner point, as an infinitely sharp corner is a non-physical feature and, thus, an unreasonable interpretation of SEO. Even in the event one might consider atomically sharp corner points, such as those found at the edge of single crystals, atoms are still known to lack infinitely sharp boundaries. As such, any physically realizable corner must comprise a smooth transition.)
an angle α2 between the slope surface and the horizontal direction (Fig. 3: left-to-right) is in a range from 20° to 40°, 40° to 60°, or 60° to 70° (As per the definition given for the slope surface, the slope surface comprises all angles from approximately 90° to 0°. Therefore, one such angle, α2, may be 65°).
Regarding Claim 8,
SEO discloses:
The LED chip as claimed claim 1,
wherein angles α1 between a side surface (the corner of SS16 where it smoothly transitions into—but before it becomes—the top flat surface of STP16) of the first step (STP16) and the horizontal direction (Fig. 3: left-to-right) decrease in a vertical direction, and the angles α1 are in a range from 10° to 30°, or 30° to 45°.
(Analogous to the argument made for Claim 7, since the side surface comprises a smooth corner, which comprises all angles from approximately 70° to 0°, we may select—as a subset—angles α1 in a range from 10° to 30° that decrease in a vertical direction.)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 15, & 17 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by TSAI (US 20160005941 A1).
Examiner’s Note
In addition to the original figures of TSAI, consider the provided annotated figure of TSAI below.
PNG
media_image3.png
590
933
media_image3.png
Greyscale
Regarding Claim 1,
TSAI discloses:
A light emitting diode (LED) chip (Fig. 19B), comprising
a semiconductor stack layer (100) and
an insulating layer (As no limitation presently requires the insulating layer to exclude a conductive layer—i.e. 200—from between constituent insulating layers of the insulating layer, 6000, 700, & 800 may together be considered an insulating layer under a broad but reasonable interpretation; hereinafter denoted 6000/700/800) disposed on the semiconductor stack layer (100); wherein the insulating layer (6000/700/800) comprises
a first insulating layer (6000) and
a second insulating layer (700) formed on an upper surface of the first insulating layer (6000),
the insulating layer (6000/700/800) has a step structure (Fig. 19B: As 6000, 700, and 800 have multiple horizontal surfaces—and corresponding sidewall surfaces—at various vertical distances from 110, 6000/700/800 as a whole may be considered to have a “step structure” under a broad but reasonable interpretation.), the step structure comprises
a first step (STP1) formed by the first insulating layer (6000) and
a second step (STP2) formed by the second insulating layer (700), and
the first step (STP1) extends beyond the second step (STP2) in a horizontal direction (Fig. 19B: left-to-right)
(As seen in Fig. 19B, nearly all of STP1 extends beyond STP2 in the horizontal direction.)
Regarding Claim 15,
TSAI discloses:
The LED chip as claimed in claim 1,
wherein the insulating layer (6000/700/800) further comprises
a third insulating layer (800) formed on an upper surface of the second insulating layer (700);
the step structure further comprises
a third step (STP3) formed by the third insulating layer (800);
a length L2 (L2, which is the entirety of the length of STP2 from left to right in Fig. 19B) of the second step (STP2) beyond the third step (STP3) in the horizontal direction (Fig. 19B: left to right) is smaller than a length L1 (L1) of the first step (STP1) beyond the second step (STP2) in the horizontal direction (Fig. 19B: left-to-right).
Regarding Claim 17,
TSAI discloses:
The LED chip as claimed in claim 15,
wherein a thickness (THK2) of the second insulating layer (700) is greater than a thickness (THK1) of the first insulating layer (6000), and
a thickness (THK3) of the third insulating layer (800) is equal to or greater than the thickness (THK2) of the second insulating layer (700); and
a density of the first insulating layer (6000, which may be silicon nitride, Par. 72) is greater than a density of the second insulating layer (700, which may be silicon oxide, Par. 75), and
(Of the various densities that are broadly but reasonably associated with 6000, one such density is the density of Si3N4 in crystalline form, which is about 3.2 g/cm3. Similarly, of the various densities that are broadly but reasonably associated with 700, one such density is the density of SiO2 in crystalline form, which is about 2.7 g/cm3. Therefore, “a” density of 6000 is greater than “a” density of 700.)
a density of the third insulating layer (800, which may be silicon oxide, Par. 77) is equal to or less than a density of the second insulating layer (700).
(Of the various densities that are broadly but reasonably associated with 800, one such density is the density of SiO2 in crystalline form, which is about 2.7 g/cm3. Therefore, “a” density of 800 is equal to the density of 700.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.S.S./Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights