DETAILED ACTION
Election/Restrictions
Applicant’s election with traverse to the restriction requirement mailed on 1/23/26 of Species 1 in the reply filed on 2/18/26 was acknowledged in a previous office action mailed on 4/2/26. Claims 4, 9, and 12 are withdrawn.
Information Disclosure Statement
The information disclosure statement filed 6/10/26 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because the Applicants’ filings with regard to the “Korean Office Action” that has been crossed out fails to comply with:
37 CFR 1.98(a)(3)(i) which requires concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language.
37 CFR 1.98(a)(2) which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed.
The IDS has been placed in the application file, but the information referred to therein having the deficiencies cited above has not been considered as to the merits, and the line has been struck out with a horizontal line. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Claim Interpretation
The Office will use the following interpretations: the term “channel pad” is not a standard term in the art, and based on the teachings of the specification and the state of the prior art, the term will be interpreted as being equivalent to a conductive pad, conductive plug, or other electrical contact or interconnection for the channel or for the source or drain regions that are typically and the end of a channel structure. Thus, it could read on e.g. a drain region, a bitline contact, a bitline, or other similar structures.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, 11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0408033 A1 (“Baraskar”).
Baraskar teaches, for example:
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Baraskar teaches:
1. A semiconductor device (see e.g. Fig. 12) comprising:
first gate electrodes (comprising e.g. “blocking dielectric layer 44,”, “metallic barrier layer 46A”, and/or “metallic fill material layer 46B”, see e.g. para 142-143) stacked on a substrate (e.g. single-crystalline III-V compound semiconductor layer 930”, see e.g. para 76), the first gate electrodes spaced apart from each other;
a first channel structure (comprising one or more parts of e.g. “vertical semiconductor channel 60”, see e.g. para 112, “memory film 50”, and “graded III-V compound semiconductor material layer 63L”) passing through the first gate electrodes, the first channel structure including:
a first channel layer (e.g. “first semiconductor channel layer 601”),
a first dielectric layer (comprising one or more of e.g. “tunneling dielectric layer 56”, “charge storage layer 54”, and “blocking dielectric layer 52”) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. “dielectric core 62”, see e.g. para 109) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. “second semiconductor channel layer 602”) covering at least a portion of the first channel layer and the first dielectric layer, and
a first channel pad (comprising one or more of 63D, 63C, 63B, and 63A, e.g. 63D/63C/63B/63A) on the first buried insulating layer; and
isolation regions (comprising one or more of e.g. “insulating layer 32” and “drain-select-level isolation structures 72”) passing through the first gate electrodes, the isolation regions spaced apart from each other (32 are spaced from each other vertically, see e.g. Fig. 12; 72 are spaced from each other laterally, see e.g. Fig. 15B),
wherein
the auxiliary channel layer is in contact with the first channel pad (see e.g. Fig. 12 wherein 602 contacts 63A),
the first channel pad is spaced apart from the first dielectric layer by the auxiliary channel layer (see e.g. Fig. 12 wherein 63A is spaced from 54/54/56 by 602), and
the first channel pad is in contact with the first buried insulating layer (see e.g. Fig. 12 wherein 63A contacts 62).
2. The semiconductor device of claim 1, wherein a width of the first channel pad (e.g. the width between the leftmost and rightmost surfaces of 63A in Fig. 12) is wider than a width between external side surfaces of the first channel layer (e.g. the side surfaces of the right part of 601 in Fig. 12).
3. The semiconductor device of claim 1, wherein the first channel pad is electrically connected to the auxiliary channel layer and the first channel layer (see e.g. Fig. 12 wherein 63A is electrically connected with 601 and 602).
8. The semiconductor device of claim 1, wherein the auxiliary channel layer is along an external side surface of the first buried insulating layer (602 is along the side of 62), an external side surface of the first channel pad (602 is along the side of the bottom part of 63A), and an internal side surface of the first channel layer (602 is along the side of 601).
11. The semiconductor device of claim 1, further comprising: a first insulating layer (this can be e.g. another one of the layers 32) on the first channel structure and the isolation regions;
a second gate electrode (this can be another of the layers 46) on the first insulating layer; and
a second channel structure passing through the second gate electrode (see Fig. 15A, wherein the overall channel structure is repeated multiple times), the second channel structure including a second channel layer, a second dielectric layer between the second channel layer and the second gate electrode, a second buried insulating layer filling an interior of the second channel layer, and a second channel pad on the second buried insulating layer (see discussion above in claim 1 for identification of these features).
Baraskar teaches:
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13. A semiconductor device (see e.g. Fig. 5J) comprising:
first gate electrodes (comprising e.g. “blocking dielectric layer 44,”, “metallic barrier layer 46A”, and/or “metallic fill material layer 46B”, see e.g. para 142-143) stacked on a substrate (e.g. single-crystalline III-V compound semiconductor layer 930”, see e.g. para 76) and apart from each other;
a first channel structure (comprising one or more parts of e.g. “vertical semiconductor channel 60”, see e.g. para 112, “memory film 50”, and “graded III-V compound semiconductor material layer 63L”) passing through the first gate electrodes, the first channel structure including:
a first channel layer (e.g. combination of “first semiconductor channel layer 601” and 63A),
a first dielectric layer (comprising one or more of e.g. “tunneling dielectric layer 56”, “charge storage layer 54”, and “blocking dielectric layer 52”) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. “dielectric core 62”, see e.g. para 109) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. “second semiconductor channel layer 602”) covering at least a portion of the first channel layer and the first dielectric layer, and
a first channel pad (comprising one or more of 63D, 63C, and 63B, e.g. 63D/63C/63B) on the first buried insulating layer; and
isolation regions (comprising one or more of e.g. “insulating layer 32” and “drain-select-level isolation structures 72”) passing through the first gate electrodes, the isolation regions spaced apart from each other (32 are spaced from each other vertically, see e.g. Fig. 5J; 72 are spaced from each other laterally, see e.g. Fig. 15B);
wherein
the auxiliary channel layer is in contact with the first channel pad (see e.g. Fig. 5J wherein 602/63A contacts 63B), an upper surface of the first dielectric layer (see e.g. Fig. 5J wherein 602/63A contacts the upper surfaces of 52/54/56), and an upper surface of the first channel layer (see e.g. Fig. 5J, wherein 602/63A contacts the upper surface of 601), and
a lower surface of the first channel pad is positioned on a level higher than an upper surface of the first channel layer (see e.g. Fig. 5J, wherein the lower surface of 63B is higher than the upper surface of 602).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baraskar.
Re claim 6, Baraskar teaches claim 1, as discussed above, and further teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein a thickness of the auxiliary channel layer is different from a thickness of the first channel layer (see Fig. 12; see e.g. para 105 wherein 602 may be 2-10 nm thick, and wherein the thickness of each layer of 63A-63D is able to be optimized, see para 114).
Applicant has not disclosed that the claimed size is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984); To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baraskar in view of US 2020/0203371 A1 (“Lee”).
Baraskar teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
19. A data storage system (see e.g. Fig. 5J) comprising: a semiconductor storage device including an upper substrate (e.g. single-crystalline III-V compound semiconductor layer 930”, see e.g. para 76), first gate electrodes (comprising e.g. “blocking dielectric layer 44,”, “metallic barrier layer 46A”, and/or “metallic fill material layer 46B”, see e.g. para 142-143) stacked on the upper substrate and spaced apart from each other,
a first channel structure (comprising one or more parts of e.g. “vertical semiconductor channel 60”, see e.g. para 112, “memory film 50”, and “graded III-V compound semiconductor material layer 63L”) passing through the first gate electrodes, and
isolation regions (comprising one or more of e.g. “insulating layer 32” and “drain-select-level isolation structures 72”) passing through the first gate electrodes and spaced apart from each other, and
wherein the first channel structure includes
a first channel layer (e.g. “first semiconductor channel layer 601”),
a first dielectric layer (comprising one or more of e.g. “tunneling dielectric layer 56”, “charge storage layer 54”, and “blocking dielectric layer 52”) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. “dielectric core 62”, see e.g. para 109) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. “second semiconductor channel layer 602”) covering at least a portion of the first channel layer and the first dielectric layer, and
a first channel pad (comprising one or more of 63D, 63C, 63B, and 63A, e.g. 63D/63C/63B/63A) on the first buried insulating layer,
the auxiliary channel layer is in contact with the first channel pad (see e.g. Fig. 5J wherein 602 contacts 63A), an upper surface of the first dielectric layer (see e.g. Fig. 5J wherein 602/63A contacts the upper surfaces of 52/54/56), and an upper surface of the first channel layer (see e.g. Fig. 5J, wherein 602/63A contacts the upper surface of 601), and
a lower surface of the first channel pad is at a level higher than an upper surface of the first channel layer (see e.g. Fig. 5J).
Baraskar does not explicitly teach:
a lower substrate,
circuit elements on one side of the lower substrate,
that the upper substrate is on the circuit elements,
an input/output pad electrically connected to the circuit elements; or
a controller electrically connected to the semiconductor storage device through the input/output pad, the controller controlling the semiconductor storage device.
Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Baraskar
a lower substrate (e.g. 201),
circuit elements (e.g. 230) on one side of the lower substrate,
that the upper substrate is on the circuit elements (see e.g. Fig. 4),
an input/output pad (e.g. a pad connecting to 250) electrically connected to the circuit elements; and
a controller electrically connected to the semiconductor storage device through the input/output pad, the controller controlling the semiconductor storage device (see e.g. para 59, wherein electrical signals may be applied to 230, the devices 230 may be connected to transistors in the memory cells).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lee to the invention of Baraskar. The motivation to do so is that the combination produces the predictable results of providing the device with a peripheral region (see e.g. para 57-59) including devices and wiring structures necessary to access the cell region of the memory device.
Baraskar and Lee together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
20. The data storage system of claim 19, wherein the auxiliary channel layer is along an external side surface of the first buried insulating layer, an external side surface of the first channel pad, and an internal side surface of the first channel layer (see e.g. Fig. 5J).
Allowable Subject Matter
Claim(s) 7, 10, 14, and 15-18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 7, 10, 14, or 15, including:
(claim 7)
the first channel structure including a first dielectric layer between the first channel layer and the first gate electrodes, a first buried insulating layer filling an interior of the first channel layer, an auxiliary channel layer covering at least a portion of the first channel layer and the first dielectric layer, and a first channel pad on the first buried insulating layer; and
wherein the auxiliary channel layer is in contact with the first channel pad, the first channel pad is spaced apart from the first dielectric layer by the auxiliary channel layer, and the first channel pad is in contact with the first buried insulating layer,
wherein an upper surface of the first dielectric layer is on a level same as an upper surface of the first channel layer.
(claim 10)
the first channel structure including a first dielectric layer between the first channel layer and the first gate electrodes, a first buried insulating layer filling an interior of the first channel layer, an auxiliary channel layer covering at least a portion of the first channel layer and the first dielectric layer, and a first channel pad on the first buried insulating layer; and
wherein the auxiliary channel layer is in contact with the first channel pad, the first channel pad is spaced apart from the first dielectric layer by the auxiliary channel layer, and the first channel pad is in contact with the first buried insulating layer,
wherein the first buried insulating layer includes a first region at a same level as the first channel layer, and a second region at a higher level than the first channel layer, and a first width of the first region is less than a second width of the second region.
(claim 14)
the first channel structure including a first dielectric layer between the first channel layer and the first gate electrodes, a first buried insulating layer filling an interior of the first channel layer, an auxiliary channel layer covering at least a portion of the first channel layer and the first dielectric layer, and a first channel pad on the first buried insulating layer; and
wherein
the auxiliary channel layer is in contact with the first channel pad, an upper surface of the first dielectric layer, and an upper surface of the first channel layer, and
a lower surface of the first channel pad is positioned on a level higher than an upper surface of the first channel layer,
wherein an upper surface of the auxiliary channel layer is on a same level as an upper surface of the first channel pad.
(claim 15)
the first channel structure including a first dielectric layer between the first channel layer and the first gate electrodes, a first buried insulating layer filling an interior of the first channel layer, an auxiliary channel layer covering at least a portion of the first channel layer and the first dielectric layer, and a first channel pad on the first buried insulating layer; and
wherein
the auxiliary channel layer is in contact with the first channel pad, an upper surface of the first dielectric layer, and an upper surface of the first channel layer, and
a lower surface of the first channel pad is positioned on a level higher than an upper surface of the first channel layer,
wherein
the first dielectric layer includes a first layer and a second layer sequentially stacked from the first channel layer, and
a first length between an upper surface of the first channel pad and an upper surface of the second layer is less than or equal to a second length between the upper surface of the first channel pad and an upper surface of the first layer.
The other claims 16-18 each depend from claim 15, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered.
Re claims 1, 13, and 19, the Office does not maintain the previously-applied rejections over Kim because Kim does not teach “the first channel pad is in contact with the first buried insulating layer” (claim 1) or “the auxiliary channel layer is in contact with the first channel pad, an upper surface of the first dielectric layer, and an upper surface of the first channel layer” (claims 13 and 19).
Re claims 1, 13, and 19, with respect to the previously-applied rejections over Baraskar, Applicant argues that the previous office action asserted certain element numbers for certain claimed elements, when in fact the Office Action made clear that most claimed elements may read on many different layers, and made extensive use of comments about the subject and “e.g.” before the element mapping. See the rejection above, where new mappings are made, and thus the arguments are not persuasive.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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