DETAILED ACTION
Election/Restrictions - TRAVERSE
A restriction requirement was mailed on 1/23/26.
Applicant's election with traverse of Species 1 in the reply filed on 2/18/26 is acknowledged. The traversal is on the ground(s) that the species “share common core elements” so there is no serious burden to search for them all. This is not found persuasive because all species, by definition, chare common core elements of a generic genus; for example, lions, tigers, jaguars, and leopards are all species of the genus Panthera, and all share common core elements, though they all are clearly different species. As noted in the restriction requirement (see sections 2 and 4), the species do have a serious burden to be searched for to find the different elements. Further, applicants claim species 1 and 3 are not mutually exclusive because of shared claimed elements. This is not found persuasive because species are not defined by the claims (see e.g. MPEP 806.04(e)).
The requirement is still deemed proper and is therefore made FINAL. Claims 4, 9, and 12 are withdrawn. Applicant noted claims 15-18 also should be withdrawn, but claims 15-18 also read on the elected embodiment, see para 36 and Fig. 2C.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/18/23 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor memory device having multilayered channel connecting to channel pad
Claim Interpretation
The Office will use the following interpretations: the term “channel pad” is not a standard term in the art, and based on the teachings of the specification and the state of the prior art, the term will be interpreted as being equivalent to a conductive pad, conductive plug, or other electrical contact or interconnection for the channel or for the source or drain regions that are typically and the end of a channel structure. Thus, it could read on e.g. a drain region, a bitline contact, a bitline, or other similar structures.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 8, 11, and 13-18 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0408033 A1 (“Baraskar”).
Baraskar teaches, for example:
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Baraskar teaches:
1. A semiconductor device (see e.g. Fig. 12) comprising:
first gate electrodes (comprising e.g. “blocking dielectric layer 44,”, “metallic barrier layer 46A”, and/or “metallic fill material layer 46B”, see e.g. para 142-143) stacked on a substrate (e.g. single-crystalline III-V compound semiconductor layer 930”, see e.g. para 76), the first gate electrodes spaced apart from each other;
a first channel structure (comprising one or more parts of e.g. “vertical semiconductor channel 60”, see e.g. para 112, “memory film 50”, and “graded III-V compound semiconductor material layer 63L”) passing through the first gate electrodes, the first channel structure including:
a first channel layer (comprising one or more of e.g. “first semiconductor channel layer 601” and/or “second semiconductor channel layer 602”),
a first dielectric layer (comprising one or more of e.g. “tunneling dielectric layer 56”, “charge storage layer 54”, and “blocking dielectric layer 52”) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. “dielectric core 62”, see e.g. para 109) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. comprising one or more layers of 63A, 63B, and 602; 602 to be considered part of the auxiliary channel layer only if the first channel layer is interpreted only as 601) covering at least a portion of the first channel layer and the first dielectric layer, and
a first channel pad (comprising one or more of 63D, 63C, 63B, and 63A, depending on the interpretation of the auxiliary channel layer) on the first buried insulating layer,
(as noted above, the disclosure has many layers, and thus many different possibilities exist for interpreting the “first channel layer”, the “first dielectric layer”, the “first buried insulating layer”, the auxiliary channel layer”, and the “first channel pad”; many of the different interpretations will read on the claimed structure; the rejection is not limited to this, but in order for the sake of concrete discussion, to provide one specific interpretation, the first channel layer may be 602, the first dielectric layer may be 52/54/56, the first buried insulating layer may be 62, the auxiliary channel layer may be 63A, and the first channel pad may be 63D/63C/63B); and
isolation regions (comprising one or more of e.g. “insulating layer 32” and “drain-select-level isolation structures 72”) passing through the first gate electrodes, the isolation regions spaced apart from each other (32 are spaced from each other vertically, see e.g. Fig. 12; 72 are spaced from each other laterally, see e.g. Fig. 15B),
wherein the auxiliary channel layer is in contact with the first channel pad (see e.g. Fig. 12), and the first channel pad is spaced apart from the first dielectric layer by the auxiliary channel layer (see e.g. Fig. 12).
2. The semiconductor device of claim 1, wherein a width of the first channel pad (e.g. the width between the leftmost and rightmost surfaces of 63B in Fig. 12) is wider than a width between external side surfaces (e.g. the “external” surfaces of 602 are those that face 62; the width between these is the same as the width of 62, which is thinner than the width identified above) of the first channel layer.
3. The semiconductor device of claim 1, wherein the first channel pad is electrically connected to the auxiliary channel layer and the first channel layer (see e.g. Fig. 12).
5. The semiconductor device of claim 1, wherein the auxiliary channel layer conformally covers an upper surface of the first dielectric layer and an upper surface of the first channel layer (see Fig. 5J).
8. The semiconductor device of claim 1, wherein the auxiliary channel layer is along an external side surface of the first buried insulating layer, an external side surface of the first channel pad, and an internal side surface of the first channel layer (see Fig. 12).
11. The semiconductor device of claim 1, further comprising: a first insulating layer (this can be e.g. another one of the layers 32) on the first channel structure and the isolation regions;
a second gate electrode (this can be another of the layers 46) on the first insulating layer; and
a second channel structure passing through the second gate electrode (see Fig. 15A, wherein the overall channel structure is repeated multiple times), the second channel structure including a second channel layer, a second dielectric layer between the second channel layer and the second gate electrode, a second buried insulating layer filling an interior of the second channel layer, and a second channel pad on the second buried insulating layer (see discussion above in claim 1 for identification of these features).
13. A semiconductor device (see e.g. Fig. 12) comprising:
first gate electrodes (comprising e.g. “blocking dielectric layer 44,”, “metallic barrier layer 46A”, and/or “metallic fill material layer 46B”, see e.g. para 142-143) stacked on a substrate (e.g. single-crystalline III-V compound semiconductor layer 930”, see e.g. para 76) and apart from each other;
a first channel structure (comprising one or more parts of e.g. “vertical semiconductor channel 60”, see e.g. para 112, “memory film 50”, and “graded III-V compound semiconductor material layer 63L”) passing through the first gate electrodes, the first channel structure including:
a first channel layer (comprising one or more of e.g. “first semiconductor channel layer 601” and/or “second semiconductor channel layer 602”),
a first dielectric layer (comprising one or more of e.g. “tunneling dielectric layer 56”, “charge storage layer 54”, and “blocking dielectric layer 52”) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. “dielectric core 62”, see e.g. para 109) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. comprising one or more layers of 63A, 63B, and 602; 602 to be considered part of the auxiliary channel layer only if the first channel layer is interpreted only as 601) covering at least a portion of the first channel layer and the first dielectric layer, and
a first channel pad (comprising one or more of 63D, 63C, 63B, and 63A, depending on the interpretation of the auxiliary channel layer) on the first buried insulating layer,
(as noted above, the disclosure has many layers, and thus many different possibilities exist for interpreting the “first channel layer”, the “first dielectric layer”, the “first buried insulating layer”, the auxiliary channel layer”, and the “first channel pad”; many of the different interpretations will read on the claimed structure; the rejection is not limited to this, but in order for the sake of concrete discussion, to provide one specific interpretation, the first channel layer may be 602, the first dielectric layer may be 52/54/56, the first buried insulating layer may be 62, the auxiliary channel layer may be 63A, and the first channel pad may be 63D/63C/63B); and
isolation regions (comprising one or more of e.g. “insulating layer 32” and “drain-select-level isolation structures 72”) passing through the first gate electrodes, the isolation regions spaced apart from each other (32 are spaced from each other vertically, see e.g. Fig. 12; 72 are spaced from each other laterally, see e.g. Fig. 15B);
wherein the auxiliary channel layer is in contact with the first channel pad (see e.g. Fig. 12), and a lower surface of the first channel pad is positioned on a level higher than an upper surface of the first channel layer (see e.g. Fig. 12).
14. The semiconductor device of claim 13, wherein an upper surface of the auxiliary channel layer is on a same level as an upper surface of the first channel pad (see e.g. Fig. 12).
15. The semiconductor device of claim 13, wherein
the first dielectric layer includes a first layer (e.g. one of 56, 54, and 52) and a second layer (e.g. another one of 56, 54, and 52) sequentially stacked from the first channel layer (e.g. 56 and 54; or 54 and 52; or 56 and 52), and
a first length between an upper surface of the first channel pad and an upper surface of the second layer is less than or equal to a second length between the upper surface of the first channel pad and an upper surface of the first layer (see e.g. Fig. 12, wherein the first length is zero, and the second length is zero).
16. The semiconductor device of claim 15, wherein the second length is less than or equal to a third length between the upper surface of the first channel pad and the upper surface of the first channel layer (see e.g. Fig. 12, wherein the second length is zero, and there is a non-zero finite third distance between the upper surface of 63D and the upper surface of 602).
17. The semiconductor device of claim 15, wherein the first dielectric layer further includes a third layer (e.g. 52, when the other two layers are 56 and 54) between side surfaces of the first gate electrodes and the second layer.
18. The semiconductor device of claim 17, wherein the third layer is coplanar with an upper surface of the auxiliary channel layer and the upper surface of the first channel pad (see Fig. 12).
Claim(s) 1, 3, 6-7, 10-11, and 13-18 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2019/0057975 A1 (“Kim”).
Kim teaches, for example:
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1. A semiconductor device (see e.g. Figs. 2A and 2B) comprising:
first gate electrodes (e,g. CG, SG1, SG2) stacked on a substrate (see para 100), the first gate electrodes spaced apart from each other;
a first channel structure (e.g. one or more layers of CH and possibly also containing ML) passing through the first gate electrodes, the first channel structure including
a first channel layer (e.g. SE1B, or SE1A/SE1B),
a first dielectric layer (e.g. one or more of TI, DL, and BL1; e.g. TI/DL/BI1) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. core insulating layer CO) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. SE2) covering at least a portion of the first channel layer and the first dielectric layer (SE2 covers the top of SE1A and the bottom of SE1B in e.g. Fig. 2A, and covers inner surfaces of ML), and
a first channel pad (e.g. “doped semiconductor layer DP”) on the first buried insulating layer; and
isolation regions (e.g. IL1, IL2) passing through the first gate electrodes (see locations of IL1 and IL2 in e.g. Figs. 2A-2B and thus infer where they would be located in Figs. 3A-3C), the isolation regions spaced apart from each other (see e.g. Fig. 2A-2B),
wherein
the auxiliary channel layer is in contact with the first channel pad (see e.g. Figs. 2A-2B), and
the first channel pad is spaced apart from the first dielectric layer by the auxiliary channel layer (see e.g. Figs. 2A-2B).
3. The semiconductor device of claim 1, wherein the first channel pad is electrically connected to the auxiliary channel layer and the first channel layer (see e.g. Figs. 2A-2B).
6. The semiconductor device of claim 1, wherein a thickness of the auxiliary channel layer is different from a thickness of the first channel layer (see e.g. Figs. 2A-2B).
7. The semiconductor device of claim 1, wherein an upper surface of the first dielectric layer is on a level same as an upper surface of the first channel layer (see e.g. Figs. 2A-2B).
10. The semiconductor device of claim 1, wherein the first buried insulating layer includes a first region at a same level as the first channel layer (e.g. a lower portion of CO in e.g. Fig. 2A), and a second region at a higher level than the first channel layer (e.g. an upper portion of CO in e.g. Fig. 2A), and a first width of the first region is less than a second width of the second region (see e.g. Fig. 2A wherein C) is wider at its top than it is at its bottom).
11. The semiconductor device of claim 1, further comprising: a first insulating layer on the first channel structure and the isolation regions (e.g. another one of IL1); a second gate electrode on the first insulating layer (e.g. another one of CG, SG1, or SG2); and a second channel structure (see in e.g. Figs. 3A-3C wherein the structure of Figs. 2A-2B would be repeated multiple times laterally across the device) passing through the second gate electrode, the second channel structure including (see discussion of claim 1 for the following elements) a second channel layer, a second dielectric layer between the second channel layer and the second gate electrode, a second buried insulating layer filling an interior of the second channel layer, and a second channel pad on the second buried insulating layer.
13. A semiconductor device comprising:
first gate electrodes (e,g. CG, SG1, SG2) stacked on a substrate (see para 100) and apart from each other;
a first channel structure (e.g. one or more layers of CH and possibly also containing ML) passing through the first gate electrodes, the first channel structure including
a first channel layer (e.g. SE1A),
a first dielectric layer (e.g. one or more of TI, DL, and BL1; e.g. TI/DL/BI1) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. core insulating layer CO) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. SE1B and/or SE2) covering at least a portion of the first channel layer and the first dielectric layer (SE2 covers the top of SE1A and the bottom of SE1B in e.g. Fig. 2A, and covers inner surfaces of ML), and
a first channel pad (e.g. “doped semiconductor layer DP”) on the first buried insulating layer; and
isolation regions (e.g. IL1, IL2) passing through the first gate electrodes, the isolation regions spaced apart from each other (see e.g. Fig. 2A-2B);
wherein
the auxiliary channel layer is in contact with the first channel pad (see e.g. Figs. 2A-2B), and
a lower surface of the first channel pad is positioned on a level higher than an upper surface of the first channel layer (see e.g. Figs. 2A-2B).
14. The semiconductor device of claim 13, wherein an upper surface of the auxiliary channel layer is on a same level as an upper surface of the first channel pad (see e.g. Figs. 2A-2B).
15. The semiconductor device of claim 13, wherein
the first dielectric layer includes a first layer and a second layer sequentially stacked from the first channel layer (see layers TI, DL, and BI1), and
a first length between an upper surface of the first channel pad and an upper surface of the second layer (see e.g. Fig. 2A, wherein the first length is zero) is less than or equal to a second length between the upper surface of the first channel pad and an upper surface of the first layer (see e.g. Fig. 2A, wherein the second length is zero).
16. The semiconductor device of claim 15, wherein the second length is less than or equal to a third length between the upper surface of the first channel pad and the upper surface of the first channel layer (see e.g. Fig. 2A, wherein the second and third lengths are zero).
17. The semiconductor device of claim 15, wherein the first dielectric layer further includes a third layer between side surfaces of the first gate electrodes and the second layer (see layers TI, DL, and BI1).
18. The semiconductor device of claim 17, wherein the third layer is coplanar with an upper surface of the auxiliary channel layer and the upper surface of the first channel pad (see e.g. Fig. 2A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baraskar.
Re claim 6, Baraskar teaches claim 1, as discussed above, and further teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein a thickness of the auxiliary channel layer is different from a thickness of the first channel layer (see Fig. 12; see e.g. para 105 wherein 602 may be 2-10 nm thick, and wherein the thickness of each layer of 63A-63D is able to be optimized, see para 114).
Applicant has not disclosed that the claimed size is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984); To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baraskar in view of US 2020/0203371 A1 (“Lee”).
Baraskar teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
19. A data storage system (see e.g. Fig. 12) comprising: a semiconductor storage device including an upper substrate (e.g. single-crystalline III-V compound semiconductor layer 930”, see e.g. para 76), first gate electrodes (comprising e.g. “blocking dielectric layer 44,”, “metallic barrier layer 46A”, and/or “metallic fill material layer 46B”, see e.g. para 142-143) stacked on the upper substrate and spaced apart from each other,
a first channel structure (comprising one or more parts of e.g. “vertical semiconductor channel 60”, see e.g. para 112, “memory film 50”, and “graded III-V compound semiconductor material layer 63L”) passing through the first gate electrodes, and
isolation regions (comprising one or more of e.g. “insulating layer 32” and “drain-select-level isolation structures 72”) passing through the first gate electrodes and spaced apart from each other, and
wherein the first channel structure includes
a first channel layer (comprising one or more of e.g. “first semiconductor channel layer 601” and/or “second semiconductor channel layer 602”),
a first dielectric layer (comprising one or more of e.g. “tunneling dielectric layer 56”, “charge storage layer 54”, and “blocking dielectric layer 52”) between the first channel layer and the first gate electrodes,
a first buried insulating layer (e.g. “dielectric core 62”, see e.g. para 109) filling an interior of the first channel layer,
an auxiliary channel layer (e.g. comprising one or more layers of 63A, 63B, and 602; 602 to be considered part of the auxiliary channel layer only if the first channel layer is interpreted only as 601) covering at least a portion of the first channel layer and the first dielectric layer, and
a first channel pad (comprising one or more of 63D, 63C, 63B, and 63A, depending on the interpretation of the auxiliary channel layer) on the first buried insulating layer,
the auxiliary channel layer is in contact with the first channel pad (see e.g. Fig. 12), and
a lower surface of the first channel pad is at a level higher than an upper surface of the first channel layer (see e.g. Fig. 12).
Baraskar does not explicitly teach:
a lower substrate,
circuit elements on one side of the lower substrate,
that the upper substrate is on the circuit elements,
an input/output pad electrically connected to the circuit elements; or
a controller electrically connected to the semiconductor storage device through the input/output pad, the controller controlling the semiconductor storage device.
Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Baraskar
a lower substrate (e.g. 201),
circuit elements (e.g. 230) on one side of the lower substrate,
that the upper substrate is on the circuit elements (see e.g. Fig. 4),
an input/output pad (e.g. a pad connecting to 250) electrically connected to the circuit elements; and
a controller electrically connected to the semiconductor storage device through the input/output pad, the controller controlling the semiconductor storage device (see e.g. para 59, wherein electrical signals may be applied to 230, the devices 230 may be connected to transistors in the memory cells).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lee to the invention of Baraskar. The motivation to do so is that the combination produces the predictable results of providing the device with a peripheral region (see e.g. para 57-59) including devices and wiring structures necessary to access the cell region of the memory device.
Baraskar and Lee together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
20. The data storage system of claim 19, wherein the auxiliary channel layer is along an external side surface of the first buried insulating layer, an external side surface of the first channel pad, and an internal side surface of the first channel layer (see e.g. Fig. 12).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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