DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tao et al. (PG Pub. No. US 2005/0233571 A1) in view of Magerlein et al. (PG Pub. No. US 2004/0084782 A1).
Regarding claim 1, Tao teaches an interconnect substrate (fig. 11) comprising:
an passivation layer (¶ 0020: 132);
an electrode (¶ 0020: 150) disposed on the passivation layer and having a first surface not covered with the passivation layer (fig. 11: top surface of 150 exposed from 132); and
an external connection terminal (¶ 0020: bump 160) disposed on the first surface of the electrode (fig. 11: 160 disposed on top surface of 150);
wherein the electrode has a recess in the first surface (fig. 11: top surface of 150 recessed),
wherein the external connection terminal includes a first conductor (¶ 0024: 146) filling the recess (fig. 11: 146 fills recess of 150) and a second conductor (¶ 0027: 148) disposed on the first conductor (fig. 11: 148 disposed in 146), and a melting point of the first conductor is higher than a melting point of the second conductor (¶ 0024: melting point of 146 higher than melting point of 148).
Tao further teaches the first conductor comprises a metal material (¶ 0024), and the first and second conductors are formed by electroplating (¶ 0027).
However, Tao is silent to the passivation layer comprising insulating material, a metal material of the electrode is different from a metal material of the first conductor, wherein the first conductor has an upper surface flush with an upper surface of the electrode, or protrudes beyond the upper surface of the electrode without being in contact with the upper surface of the electrode.
Magerlein teaches an interconnect substrate including a passivation layer (16) comprising insulating material (¶ 0027: 16 comprises a passivation dielectric), an electrode (15, 17 and/or 20) comprising metal material (¶ 0014: 15, 17 and 20 comprise various metals), and an external connection terminal (¶ 0014: 22) disposed on the first surface of the electrode (figs. 1, 3: 22 disposed on top surface of 15/17/20), a metal material of the electrode is different from a metal material of the first conductor (¶ 0014: metal material of 15, 17 and/or 20 different from metal material of 22).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the interconnect substrate of Tao with the passivation layer and electrode materials of Magerlin, as a means to form fine solder joints with solder reaction barrier layer and a noble metal protection/solder wetting layer (Magerlin, ¶ 0008).
Magerlein further teaches wherein the first conductor has an upper surface flush with an upper surface of the electrode (figs. 1, 3: 15/17/20 has an upper surface flush with upper surface of 22), or protrudes beyond the upper surface of the electrode without being in contact with the upper surface of the electrode (figs. 1, 3: 17/20 laterally protrudes beyond upper surface of 22 without physically contacting the upper surface of 22).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first conductor upper surface of Tao to be flush with the upper surface of the electrode, or protrude beyond the upper surface of the electrode without being in contact with the upper surface of the electrode, as a means to provide a mating connection to the solder microjoints, and/or provide a current suitable for a plating process (Magerlein, ¶ 0014).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the materials of Magerlein are suitable to form structure of Tao.
Regarding claim 3, Tao in view of Magerlein teaches the interconnect substrate as claimed in claim 1, wherein the first conductor and the second conductor are solder (Tao, ¶ 0027).
Regarding claim 4, Tao in view of Magerlein teaches the interconnect substrate as claimed in claim 1, wherein the first conductor is a metal sintered material, and the second conductor is solder (Tao, ¶ 0027 & Magerlein, ¶ 0014).
Should applicant traverse on the grounds that the limitation of “the first conductor is a metal sintered material” is patentably distinct from the claim 3 limitation “the first conductor…[is] solder”, Applicant should submit evidence or identify such evidence now of record showing the inventions to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
Regarding claim 5, Tao in view of Magerlein teaches the interconnect substrate as claimed in claim 1, wherein the electrode (Tao, 150) includes a pad disposed on one surface of the insulating layer (Tao, fig. 11: at least upper portion of 150 disposed on a surface of 132) and a through interconnect connected to the pad and disposed in the insulating layer (Tao, fig. 11: second portion of 150 disposed in 132), and
wherein the recess is formed in the pad and extends from the pad to the through interconnect (Tao, fig. 11: recess formed in upper portion of 150 and extends to embedded portion of 150).
Regarding claim 6, Tao in view of Magerlein teaches the interconnect substrate as claimed in claim 5, wherein the through interconnect protrudes from an opposite surface of the insulating layer to serve as a second external connection terminal (Tao, fig. 11: vertical portion of 150 extends through 132 and provide external connection to bond pad 124).
Regarding claim 7, Tao in view of Magerlein teaches a semiconductor apparatus (Tao, figs. 2-3 among others) comprising:
the interconnect substrate of claim 5 (Tao, fig. 11); and
a semiconductor chip (Tao, ¶ 0020: 120) mounted in an opposing relationship to the one surface of the insulating layer and electrically connected to the external connection terminal (Tao, figs. 2-5b: 120 mounted opposite to pad portion of 150 and electrically connected to 124).
Regarding claim 10, Tao in view of Magerlein teaches the interconnect substrate as claimed in claim 1, wherein the second conductor (Tao, 148) is in contact with the upper surface of the electrode around a periphery of the first conductor (Tao, fig. 5b: 148 in at least electrical contact with upper surface of 150 around a periphery of 146).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tao in view of Magerlein as applied to claim 1 above, and further in view of Nakamura (PG Pub. No. US 2001/0014005 A1).
Regarding claim 2, Tao in view of Magerlein teaches the interconnect substrate as claimed in claim 1, comprising first and second conductors (Tao, 146 & 148). Tao in view of Aoki further teaches the first conductor includes a lower composition of tin (Tao, ¶ 0024).
Tao in view of Magerlein does not teach wherein a specific resistance of the first conductor is higher than a specific resistance of the second conductor.
Nakamura teaches that specific resistance of lead is higher than tin (¶ 0019).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the specific resistance of the first and second conductors of Tao in view of Aoki, as a means to optimize the respective melting points of each material (Nakamura, ¶ 0019).
Furthermore, said artisan would recognize that the first conductor composition with lower content of tin would have lower specific resistance relative to the second conductor composition, as evidenced by Nakamura.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tao in view of Magerlein as applied to claim 6 above, and further in view of Kim et al. (PG Pub. No. US 2023/0034654 A1).
Regarding claim 8, Tao in view of Magerlein teaches a semiconductor apparatus (Tao, figs. 2-3 among others) comprising:
the interconnect substrate of claim 6 (Tao, fig. 11); and
a semiconductor chip (Tao, ¶ 0020: 120) electrically connected to the second external connection terminal (Tao, figs. 2-5b: 120 electrically connected exposed portion of 150).
Tao in view of Magerlein does not explicitly teach the semiconductor chip is mounted in an opposing relationship to the opposite surface of the insulating layer.
Kim teaches a semiconductor apparatus (fig. 3) including a semiconductor chip (¶ 0047: 110) mounted in an opposing relationship to the opposite surface of an insulating layer (¶ 0056 figs. 2-3 among others: 110 mounted opposite to insulating layer 222).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor apparatus of Tao in view of Magerlein to further including an opposing semiconductor die, as a means to provide a multi-chip semiconductor package (Kim, ¶ 0093), improving device functionality.
Regarding claim 9, Tao in view of Magerlein and Kim teaches the semiconductor apparatus as claimed in claim 8, further comprising a bus bar (Kim, ¶ 0056: wirings 224a/224b/224c) electrically connected to the external connection terminal (Kim, fig. 3: 224a-224c electrically connected to external connection terminal 290, equivalent to 160 of Tao).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kirby (PG Pub. No. US 2019/0131260 A1) teaches an interconnect substrate (110), wherein a second conductor (123) is in physical contact an upper surface of an electrode (124) around a periphery of a first conductor (fig. 1: 124 contacts surface of 124 around a periphery of first conductor 121) as recited in claim 10.
Chandrasekaran et al. (PG Pub. No. US 2012/0012998 A1) teaches an interconnect substrate (202) including a first conductor (212/220) with an upper surface flush with an upper surface of an electrode (fig. 2H: upper surface of 212/220 flush with edges of upper surface of 222), or protrudes beyond the upper surface of the electrode without being in contact with the upper surface of the electrode (fig. 2H: 212/220 laterally protrudes beyond upper surface of 222) as recited in claim 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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