DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/18/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: numeral 121 in fig. 2A is not described in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19/293,574 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other as described below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant claim
Reference claim
reasoning
1
1
Substantially the same. Reference claim has the gate structure on a channel region whereas instant claim has it on a substrate, but channel regions are known to be in substrates.
2
2
Substantially similar
3
3
Substantially similar
4
4
Substantially similar
5
5
Substantially similar
6
6
Substantially similar
7
7
Substantially similar
8
1
Determining optimal ratio would be obvious.
9
8
Substantially similar
10
9
Reference claim is narrower than the instant claim, thus the instant claim is anticipated.
11
10
Substantially similar
12
11
Substantially similar
13
12
Substantially similar
14
13
Substantially similar
15
14
Substantially similar
16
15
Substantially similar
17
16
Reference claim is narrower than the instant claim, thus the instant claim is anticipated.
18
17
Substantially similar
19
18
Reference claim teaches conformally depositing a dielectric layer on the second and third S/D structures but does not explicitly teach removing the dielectric material on the third S/D. However, the S/D contact structure makes contact with the third S/D structure, thus it is obvious the dielectric layer would need to be removed over the third S/D structure.
20
20
Substantially similar
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 8,10, 11,15 and 17-19 are rejected under 35 U.S.C. 103 as being obvious over Lin (US 2023/0065045). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under both 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2).
As to claim 1, Lin teaches a semiconductor structure (annotated fig. 15 below), comprising:
a gate structure (314/315) on a substrate (302, [0027]);
first and second source/drain (S/D) structures (see below) on opposite sides of the gate structure (314/315, [0029], there are multiple gate structures and multiple S/D structures that would continue on, even if not shown);
an isolation layer (330/333) on the second S/D structure (329, [0032]);
a third S/D structure (328) adjacent to and separate from the second S/D structure (329, [0032]); and
a S/D contact structure (340) on the isolation layer (330/333) and the third S/D structure (328, [0040]),
wherein the isolation layer (330/333) separates the S/D contact structure (240) from the second S/D structure (329).
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544
790
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As to claim 3, Lin further teaches a silicide layer on the third S/D structure, wherein the silicide layer is in contact with the third S/D structure and the S/D contact structure ([0029]).
As to claim 7, Lin further teaches an additional S/D contact structure on the first S/D structure ([0042], other contacts will be formed). Lin does not teach a distance between bottom surfaces of the additional S/D contact structure and the isolation layer ranges from about 2 nm to about 10 nm. However, determining the heights of the additional S/D contact structures and the isolation layer is necessary and minimizing them would have been obvious so as to reduce the size of the device. If that leads to a distance between 2nm and 10nm then that is the result of ordinary skill in the art and not innovation.
As to claim 8, see optimization and minimization argument above.
As to claims 10 and 17, Lin teaches a semiconductor device (see annotated fig. 15 below), comprising:
a first transistor (see below) on a substrate, wherein the first transistor comprises first and second source/drain (S/D) structures (see below, [0029]);
a second transistor (see below) on the substrate, wherein the second transistor comprises a third S/D structure (328) adjacent to the second S/D structure (329, [0032]);
an isolation layer (330/333) on the second S/D structure (329, [0032]); and
a S/D contact structure (340) extending over the second and third S/D structures (328 and 329, [0040]),
wherein:
the third S/D structure (328) is electrically connected to the S/D contact structure (340), and
the isolation layer (330/333) isolates the second S/D structure (329) from the S/D contact structure (340).
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As to claim 11, Lin further teaches a silicide layer on the third S/D structure, wherein the silicide layer is in contact with the third S/D structure and the S/D contact structure ([0029]).
As to claim 15, Lin further teaches an additional S/D contact structure on the first S/D structure ([0042], other contacts will be formed and coplanarity would be obvious so as to simplify subsequent metallization formation).
As to claim 18, Lin further teaches a silicide layer on the third S/D structure, wherein the silicide layer is in contact with the third S/D structure and the S/D contact structure ([0029]).
As to claim 19, Lin further teaches forming the isolation layer comprises: conformally depositing a layer of dielectric material (330) on the second and third S/D structures (328 and 329, fig. 6, [0032]); and removing the layer of dielectric material on the third S/D structure (328, fig. 10, [0036]).
Allowable Subject Matter
Claims 2, 4-6, 9, 12-14, 16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and also if the double patenting rejection is overcome. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 2, Lin fails to teach top surfaces of the S/D contact structure and the gate structure are coplanar. Lin very clearly teaches an etch-back process for the S/D structures to have a different height from the gates.
As to claims 4, 5, 12, and 13, Lin fails to teach a portion of the silicide layer is on sidewall surfaces of the third S/D structure or an etch stop layer (ESL) on sidewall surfaces of the third S/D structure. The sidewalls of the S/D structures are not exposed during the siliciding process or during the ESL deposition process.
As to claims 6 and 14, Lin fails to teach a fourth S/D structure between the second and third S/D structures, wherein the isolation layer separates the fourth S/D structure and the S/D contact structure. There is no fourth structure between the second and third structures.
As to claims 9, 16, and 20, Lin fails to teach an additional S/D contact structure on the first S/D structure and an interconnect structure over the gate structure, wherein the S/D contact structure, the interconnect structure, and the additional S/D contact structure connect the third S/D structure to the first S/D structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
3/30/26
Prosecution Insights