DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 1-10 in the reply filed on 01/07/2026 is acknowledged. Claims 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and Species, here being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/07/2026.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2021-072819, filed on 04/22/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/18/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "first power line, second power line, and third power line" and "first local interconnect and local interconnect layer" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 2 recites the broad recitation “a first power line formed in a buried interconnect layer, the first power line extending in a first direction and supplying the first power supply voltage; a second power line formed in a first interconnect layer, the second power line extending in the first direction and supplying the first power supply voltage, and the claim also recites " the second power line overlaps the first power line in planar view, and is connected to the first power line through a via" which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102 as being anticipated by Ohtou et al. ( US 10,170,413 B2; hereinafter Ohtou )
Regarding claim 1, Ohtou teaches an output circuit ( Fig. 1 #105 ) for outputting a signal from a semiconductor integrated circuit ( Fig. 1 #100 ), comprising: a first transistor ( Fig. 1: T2 ) of a first conductivity type ( Col. 3 lines 21-23 the transistor T2 is an NMOS transistor) connected between a first power supply supplying a first power supply voltage ( Fig. 1: VSS ) and an output terminal ( Fig. 1: VOUT ); a first power line ( Fig. 2C #241 ) formed in a buried interconnect layer ( Fig. 2C: BML3 ), the first power line extending in a first direction ( as shown in Fig. 2C ) and supplying the first power supply voltage ( Col. 7 lines 3-7 the buried metal line BML3 is further electrically coupled to the power supply VSS illustrated in FIG. 1 ); a second power line ( Fig. 2C #244 ) formed in a first interconnect layer ( Col. 8 Lines 13-14 The local interconnections 243 and 244 are formed on the shallow trench isolation structure ) located above the buried interconnect layer ( Fig. 2C: BML3 ), the second power line ( Fig. 2C #244 ) extending in the first direction ( as shown in Fig. 2C ) and supplying the first power supply voltage ( Col. 8 lines 19-21 A portion of the local interconnection 244 extends to the trench 315 to be electrically coupled to the buried metal line BML3.); a third power line ( Fig. 2B: ML3 ) formed in a second interconnect layer ( Col. 8 lines 37-40 a portion of the top metal line ML3 extends through the dielectric layer 360 to be electrically coupled to the local interconnection 244 ) located above the first interconnect layer ( Col. 6 lines 25-28 In a top-down sequence, the top metal lines ML1-ML4 are formed above, for example, the transistors T1-T8, while the buried metal lines BML1-BML3 are formed under the transistors T1-T8 ), the third power line ( Fig. 2B: ML3 ) extending in a second direction perpendicular to the first direction ( as shown in Fig. 2 ) and being connected to the second power line ( as discussed above ); a first output interconnect ( Fig. 2C: C6; Col. 6 lines 50-56 The output signal Vout illustrated in FIG. 1 can be generated from the second sources/drains of the transistors T1, T3, T5 and T7 and the first sources/drains of the transistor T2, T4, T6 and T8, when, in view of FIG. 2B, the output signal Vout is transmitted through any one of the contacts C6 and C7 to the top metal line ML3 ) formed in the first interconnect layer ( Fig. 2B: ML3), the first output interconnect extending in the first direction and being connected to the output terminal ( as shown in Fig. 2B ); and a second output interconnect ( Fig. 2C: C7; as discussed above ) formed in the second interconnect layer ( Col. 8 lines 37-40 a portion of the top metal line ML3 extends through the dielectric layer 360 to be electrically coupled to the local interconnection 244 ), the second output interconnect extending in the second direction ( Fig. 2B C7 extends in the X and Y direction ) and being connected to the first output interconnect ( Fig. 2B C7 is connected to ML3 ).
Regarding claim 2, Ohtou teaches the output circuit of claim 1 ( as discussed above), wherein the second power line ( Fig. 2C #244 ) overlaps the first power line ( Fig. 2C #241 ) in planar view ( as shown in Fig. 3 ), and is connected to the first power line through a via ( Col. 6 line 66 – Col. 7 line 1 the buried metal line BML3 is electrically coupled to the local interconnections 241, 244 and 247 )
Regarding claim 3, Ohtou teaches the output circuit of claim 1 ( as discussed above), wherein the first transistor includes a plurality of FETs arranged in the second direction ( Fig. 2B: T2, T4, T6, and T8 ), the output circuit further comprises a first local interconnect ( Col. 7 lines 1-3 the second sources/drains of the transistors T2, T4, T6 and T8 are electrically coupled together.) formed in a local interconnect layer ( Col. 7 lines 3-7 the buried metal line BML3 is further electrically coupled to the power supply VSS illustrated in FIG. 1, such that the second source/drains of the transistors T2, T4, T6 and T8 receive the power supply VSS), the first local interconnect extending in the second direction ( as shown in Fig. 2C ) and being connected in common to sources of the plurality of FETs ( as discussed above ), and the first local interconnect ( as discussed above ) is connected to the first power line ( Fig. 2C #241 ) and the second power line ( Fig. 2C: BLM2; Col 6 lines 61-65 the buried metal line BML2 is further electrically coupled to the power supply VDD illustrated in FIG. 1, such that the first sources/drains of the transistors T1, T3, T5 and T7 receive the power supply VDD).
Regarding claim 4, Ohtou teaches the output circuit of claim 1 ( as discussed above ), wherein the first transistor includes a plurality of FETs arranged in the first direction (Col. 7 lines 1-3 the second sources/drains of the transistors T2, T4, T6 and T8 are electrically coupled together), the output circuit further comprises a first local interconnect ( Col. 7 lines 1-3 the second sources/drains of the transistors T2, T4, T6 and T8 are electrically coupled together ) formed in a local interconnect layer ( Col. 7 lines 3-7 the buried metal line BML3 is further electrically coupled to the power supply VSS illustrated in FIG. 1, such that the second source/drains of the transistors T2, T4, T6 and T8 receive the power supply VSS ), the first local interconnect ( as discussed above ) extending in the first direction ( as shown in Fig. 2C ) and being connected in common to sources of the plurality of FETs ( as discussed above ), and the first local interconnect ( as discussed above ) is connected to the first power line ( Fig. 2C #241 ) and the second power line ( Fig. 2C: BLM2; Col 6 lines 61-65 the buried metal line BML2 is further electrically coupled to the power supply VDD illustrated in FIG. 1, such that the first sources/drains of the transistors T1, T3, T5 and T7 receive the power supply VDD).
Regarding claim 5, Ohtou discloses the output circuit of claim 1 ( as discussed above), further comprising: a second transistor ( Fig. 2C: T4 ) of the first conductivity type ( Col. 3 lines 49-51 each one of the transistors T4, T6 and T8 is an NMOS transistor ) connected in series with the first transistor ( Fig. 2C: T2 ) between the first power supply and the output terminal ( Col. 3 line 66 – Col. 4 line 2 The second sources/drains of the transistors T1, T3, T5 and T7 and the first sources/drains of the transistors T2, T4, T6 and T8 are further electrically coupled together to generate an output signal Vout ), wherein structures of the first transistor ( Fig. 2C: T2 ) and the second transistor ( Fig. 2C: T4 ), each constituting a channel, a gate, a source, and a drain, are separated from each other ( as shown in Fig 1 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 are rejected under U.S.C. 103 as being unpatentable over Ohtou et al.; US 10,170,413 B2; 03/2017 in view of Yamagami; US 2020/0350305 A1; 07/2020
Claim 6: Ohtou teaches an output circuit ( Fig. 1 #105 ) for outputting a signal from a semiconductor integrated circuit ( Fig. 1 #100 ), comprising: a first transistor ( Fig. 1: T2 ) of a first conductivity type ( Col. 3 lines 21-23 the transistor T2 is an NMOS transistor) connected between a first power supply supplying a first power supply voltage ( Fig. 1: VSS ) and an output terminal ( Fig. 1: VOUT ); a first power line ( Fig. 2C #241 ) formed in a buried interconnect layer ( Fig. 2C: BML3 ), the first power line extending in a first direction ( as shown in Fig. 2C ) and supplying the first power supply voltage ( Col. 7 lines 3-7 the buried metal line BML3 is further electrically coupled to the power supply VSS illustrated in FIG. 1 ); a second power line ( Fig. 2C #244 ) formed in a first interconnect layer ( Col. 8 Lines 13-14 The local interconnections 243 and 244 are formed on the shallow trench isolation structure ) located above the buried interconnect layer ( Fig. 2C: BML3 ),
Ohtou does not appear to disclose the second power line extending in a second direction perpendicular to the first direction and supplying the first power supply voltage; a third power line formed in a second interconnect layer located above the first interconnect layer, the third power line extending in the first direction and being connected to the second power line; a first output interconnect formed in the first interconnect layer, the first output interconnect extending in the second direction and being connected to the output terminal; and a second output interconnect formed in the second interconnect layer, the second output interconnect extending in the first direction and being connected to the first output interconnect.
Yamagami teaches the second power line ( Fig. 2: M2 ) extending in the second direction ( [0063] The M2 interconnect 61 is connected to the gate lines 31 and 33 with an M1 interconnect 55 extending in the Y-direction ) perpendicular to the first direction ( Y is perpendicular to X ) and supplying the first power supply voltage ( [0067] an M2 interconnect 66 that supplies a power supply voltage VDD extend in the X-direction); a third power line ( Fig. 5: M3 ) formed in a second interconnect layer ( Fig. 5 #72 ) located above the first interconnect layer ( [0069] The M3 interconnect 72 serving as the inverted bit line/BL is located on the first grid on the right of the M3 interconnect 71, above the M1 interconnect 51 that supplies the power supply voltage VSS ), the third power line ( Fig. 5: M3 ) extending in a first direction ( Fig. 5: M3 interconnects extend in the Y direction ) and being connected to the second power line ( as stated above ); a first output interconnect ( Fig. 7A: node A ) formed in the first interconnect layer ( [0061] The local interconnect 41, the M1 interconnect 53, and the gate line 34 are associated with the storage node A ), the first output interconnect ( Fig. 7A: node A ) extending in the second direction and being connected to the output terminal ( [0052] The transistor PG1 is connected between the storage node A and a bit line BL ); and a second output interconnect ( Fig. 7A: node B ) formed in the second interconnect layer ( [0060] The bottom regions 14 and 15, the interconnect 21 between bottom regions, and the gate line 32 are associated with the storage node B ), the second output interconnect extending in the first direction ( Fig. 3 connections 21 and 32 are shown; 21 extends in the Y direction ) and being connected to the first output interconnect ( [0052] the transistor PG2 is connected between the storage node B and an inverted bit line/BL ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yamagami with Ohtou to implement the second power line extending in a second direction perpendicular to the first direction and supplying the first power supply voltage; a third power line formed in a second interconnect layer located above the first interconnect layer, the third power line extending in the first direction and being connected to the second power line; a first output interconnect formed in the first interconnect layer, the first output interconnect extending in the second direction and being connected to the output terminal; and a second output interconnect formed in the second interconnect layer, the second output interconnect extending in the first direction and being connected to the first output interconnect because this minimizes electrical resistance, reduces parasitic capacitance, and maximizes power efficiency.
Claim 7: Ohtou and Yamagami disclose the output circuit of claim 6 ( as discussed above).
Ohtou teaches the first transistor includes a plurality of FETs ( Col. 3 lines 49-51 each one of the transistors T4, T6 and T8 is an NMOS transistor ) arranged in the second direction ( Fig. 2B: T2, T4, T6, and T8 ), and the second power line is connected in common to sources of the plurality of FETs ( Col. 7 lines 3-7 the buried metal line BML3 is further electrically coupled to the power supply VSS illustrated in FIG. 1, such that the second source/drains of the transistors T2, T4, T6 and T8 receive the power supply VSS ).
Claim 8: Ohtou and Yamagami disclose the output circuit of claim 6 ( as discussed above).
Ohtou teaches a second transistor of a second conductivity type ( Fig. 2B: T1, T3, T5 and T7 ) connected between a second power supply supplying a second power supply voltage ( Col. 6 lines 59-61 the first sources/drains of the transistors T1, T3, T5 and T7 receive the power supply VDD ) and the output terminal ( Col. 6 lines 47-50 The output signal Vout illustrated in FIG. 1 can be generated from the second sources/drains of the transistors T1, T3, T5 and T7 ), wherein the first power line ( Fig. 2C #241 ) is placed between the first transistor and the second transistor in planar view ( Fig. 2C #241 is between T1 and T2 ).
Claim 9: Ohtou and Yamagami disclose the output circuit of claim 6 ( as discussed above).
Ohtou teaches the first transistor includes a plurality of FETs arranged in the first direction ( Fig. 2B: T2, T4, T6, and T8 ), and the second power line ( Fig. 2C #244 ) is connected in common to sources of the plurality of FETs ( Col. 6 line 66 – Col. 7 line 3 For illustration of FIG. 2C, the buried metal line BML3 is electrically coupled to the local interconnections 241, 244 and 247. Correspondingly in FIG. 1, the second sources/drains of the transistors T2, T4, T6 and T8 are electrically coupled together ).
Claim 10: Ohtou and Yamagami disclose the output circuit of claim 6 ( as discussed above).
Ohtou teaches a second transistor ( Fig. 2C: T4 ) of the first conductivity type connected in series with the first transistor ( Fig. 2C: T2 ) between the first power supply ( Fig. 1: VSS ) and the output terminal ( Fig. 1: Vout ), wherein structures of the first transistor and the second transistor, each constituting a channel, a gate, a source, and a drain, are separated from each other ( as shown in Fig. 1 ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817