DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US Pub no. 2017/0062330 A1)
Regarding claim 1, Kim et al discloses A semiconductor device, comprising:
a substrate (10)including a first region (CAR) and a second region(CTR) in a first direction from the first region(CAR)[0136] fig. 12/ fig. 13/ fig. 5d; a stack structure (ST)including electrode patterns (EL)and dielectric patterns (ILD)vertically and alternately stacked on the substrate(10)[0079]; a plurality of channels (csp)vertically penetrating the stack structure on the first region(CAR); a planarized dielectric layer (120)covering the stack structure(ST)[0142]; and a plurality of wiring patterns (CL)on the planarized dielectric layer[0143], each of the dielectric patterns(ILD) including a first dielectric pattern on the first region(CAR); and a second dielectric pattern(ILD) on the second region(CTR), each of the second dielectric patterns(ILD of ctr) including a first sub-dielectric pattern(DIL2); and a second sub-dielectric pattern (DIL1)connected in a second direction to the first sub- dielectric pattern(DIL2) fig. 5d[0099], the second direction intersecting the first direction, a dielectric constant of the first sub-dielectric patterns (DIL2)being greater than a dielectric constant of the first dielectric patterns (DIL1 of CAR)and a dielectric constant of the second sub-dielectric patterns(Dil1 of CTR)[0136][0099].
Regarding claim 2, Kim et al discloses wherein the first dielectric patterns(DIL1 of CAR) and the second sub-dielectric patterns(DIL2) include a same material[0136][0099].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2017/0062330 A1) in view of Kim (US Pub no. 2020/0321351 A1)
Regarding claim 3, Kim et al (330) discloses all the claim limitations of claim 2 but fails to teach wherein the first dielectric patterns and the second sub-dielectric patterns include silicon oxide (SiO), and the first sub-dielectric patterns include aluminum oxide (Al₂O₃), titanium oxide (TiO₂), zirconium oxide (ZrO₂), or hafnium oxide (HfO₂).
However, Kim et al (351) discloses insulative levels alternated with wordline levels in a vertical stack [0024]wherein the insulative levels comprises insulative materials 18 and 32 comprising silicon oxide and aluminum oxide (Al₂O₃), zirconium oxide (ZrO₂), or hafnium oxide (HfO₂)[0038][0065]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al (‘330) with the teachings of Kim et al (‘351) because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007)).)
Regarding claim 4, Kim et al (‘330) discloses all the claim limitations of claim 1 but fails to teach wherein interfaces between the first sub-dielectric patterns and the second sub-dielectric patterns are perpendicular to a top surface of the substrate.
However, Kim et al (‘351) discloses insulative levels alternated with wordline levels in a vertical stack [0024]wherein the insulative levels comprises laterally disposed insulative materials 18 and 32 [0037][0038]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al (330) with the teaching of Kim et al (‘351) such that interfaces between the first sub-dielectric patterns and the second sub-dielectric patterns are perpendicular to a top surface of the substrate results since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Regarding claim 5, Kim et al (‘330) discloses all the claim limitations of claim 1 but fails to teach wherein interfaces between the first sub-dielectric patterns and the second sub-dielectric patterns are bent in the second direction.
Kim et al (‘351) discloses insulative levels alternated with wordline levels in a vertical stack [0024]wherein the insulative levels comprises laterally disposed insulative materials 18 and 32 wherein the patterns are bent in the second direction fig. 16 [0037][0038]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al (330) with the teaching of Kim et al (‘351) such that interfaces between the first sub-dielectric patterns and the second sub-dielectric patterns are bent in the second direction results since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Regarding claim 6, Kim et al (‘330) discloses all the claim limitations of claim 1 but fails to teach, wherein interfaces between the first sub-dielectric patterns and the second sub-dielectric patterns become farther away in a direction opposite to the second direction as the interfaces approach closer to the substrate.
However, Kim et al (351) discloses insulative levels alternated with wordline levels in a vertical stack [0024]wherein the insulative levels comprises laterally disposed insulative materials 18 and 32 wherein the interface become farther away in a direction opposite to the second direction as the interfaces approach closer to the substrate[0037][0038]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al (330) with the teaching of Kim et al (‘351) such that wherein interfaces between the first sub-dielectric patterns and the second sub-dielectric patterns become farther away in a direction opposite to the second direction as the interfaces approach closer to the substrate results since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Claim(s) 7-8 ,12 ,13, & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2017/0062330 A1) in view of Lim (US Pub no. 20190164991 A1).
Regarding claim 7, Kim et al discloses all the claim limitations of claim 1 and further teaches wherein the substrate includes a cell array region and a connection region in the second direction from the cell array region, wherein the stack structure has a stepwise structure on the connection region, the semiconductor device further comprises a plurality of through plugs on the connection region, the through plugs penetrating the planarized dielectric layer and being connected to the electrode patterns
but fails to teach each of the wiring patterns connects two of the through plugs to each other.
However, Lim et al discloses a memory system wherein wiring patterns (UPM11/UPM12)connects two of the through plugs(edge contacts) to each other fig. 11[01109]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Lim et al to achieve a capacitive structure.
Regarding claim 8, Lim et al discloses wherein a capacitor (52)is constituted by two of the electrode patterns(edge contacts) and the dielectric patterns(52) between the two of the electrode patterns(WL1_1b /WL2_1b), the two of the electrode patterns being connected to two of the through plugs(edge contacts)[0109].
Regarding claim 12, Kim et a discloses a semiconductor device comprising a substrate (10)including a cell array region(CAR) and a connection region(CTR) in a first direction from
the cell array region(CAR) [0136], the cell array region(CAR) having a first region(CAR) and a second region (PAD region connected to VS)in a second
direction from the first region(CAR) fig. 19, the second direction being orthogonal to the first direction fig. 19; a stack structure (ST) including electrode patterns (EL)vertically stacked on the substrate(10)[0174], first dielectric patterns(ILD-DIL2)[0099]) between the electrode patterns(EL) on the first region(CAR), and second dielectric patterns(ILD-DIL1)[0099]) between the electrode patterns (EL)on the second region(PAD region connected to VS)fig. 19/fig. 5d, an end in the first direction of the stack
structure (ST)having a stepwise structure fig. 19; a plurality of channels (CSP)vertically penetrating the stack structure (ST)on the first region(CAR)[0179]; a plurality of vertical structures(VS) vertically penetrating the stack structure on the second region(PAD region connected to VS)[0176]; a planarized dielectric layer (120)covering the stack structure(ST); a plurality of through plugs(PLG) on the connection region[0181], the through plugs (PLG)penetrating the planarized dielectric layer (120)and being connected to the electrode patterns(EL)[0181]; and a plurality of wiring patterns(CL) on the planarized dielectric layer(120)[0181], the first dielectric patterns (DIL2)including a material different from a material of the second dielectric patterns(DIL1) [0099]
but fails to teach each of the wiring patterns connecting two of the through plugs to each other.
However, Lim et al discloses a memory system wherein wiring patterns (UPM11/UPM12)connects two of the through plugs(edge contacts) to each other fig. 11[01109]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Lim et al to achieve a capacitive structure.
Regarding claim 13, Kim et al discloses wherein the stack structure (ST)further includes third dielectric patterns(DIL2in CTR) between the electrode patterns (EL)
on the connection region(CTR), the third dielectric patterns(DIL2) include a material the same as the material of the first dielectric patterns (DIL2 in CAR)and different from the material of the second dielectric patterns(DIL1) [0099][0136].
Regarding claim 19,Kim et al discloses wherein a dielectric constant of the second dielectric patterns (DIL2)is greater than a dielectric constant of the first dielectric patterns(DIL1) [0099].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2017/0062330 A1) in view of Lim (US Pub no. 20190164991 A1) as applied to claim 7 and further in view of Yu ( US Patent 9,673,213 B1)
Regarding claim 9, Kim et al as modified by Lim et al discloses all the claim limitations of claim 7 but fails to teach further comprising a plurality of vertical structures on the second region, the vertical structures vertically penetrating the stack structure on the connection region, wherein the vertical structures are in contact with lateral surfaces of the first sub-dielectric patterns.
However, Yu et al discloses a plurality of vertical structures(7P) on the second region, the vertical structures(7P) vertically penetrating the stack structure (32,42)on the connection region(300), wherein the vertical structures(7P) are in contact with lateral surfaces of insulating layers of the stack structure (32,42)Col. 17, lines 23-36). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Kim et al & Lim et al with the teachings of Yu et al such that a plurality of vertical structures on the second region, the vertical structures vertically penetrating the stack structure on the connection region, wherein the vertical structures are in contact with lateral surfaces of the first sub-dielectric patterns results to provide support during subsequent processing steps.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2017/0062330 A1) in view of Lim (US Pub no. 20190164991 A1) as applied to claim 19 and further in view of Kim (US Pub no. 2020/0321351 A1)
Regarding claim 20, Kim et al(‘330) as modified by Lim et al discloses all the claim limitations of claim 19 but fails teach wherein the first dielectric patterns include silicon oxide (SiO), and the second dielectric patterns include aluminum oxide (Al₂O₃), titanium oxide (TiO₂), zirconium oxide (ZrO₂), or hafnium oxide (HfO₂).
However, Kim et al (351) discloses insulative levels alternated with wordline levels in a vertical stack [0024]wherein the insulative levels comprises insulative materials 18 and 32 comprising silicon oxide and aluminum oxide (Al₂O₃), zirconium oxide (ZrO₂), or hafnium oxide (HfO₂)[0038][0065]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al (‘330) & Lim et al with the teachings of Kim et al (‘351) because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007)).)
Allowable Subject Matter
Claim 22 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: the limitations of clam 22 including: the second dielectric patterns including a material different from a material of the first dielectric patterns and different from a material of the third dielectric patterns was not found in prior art.
Claims 10 , 11, & 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The limitation of claim 10 including: a lowermost one of the second dielectric patterns includes the first sub-dielectric pattern and does not include the second sub-dielectric pattern, and the first sub-dielectric pattern of the lowermost second dielectric pattern extends below the second sub-dielectric pattern of another second dielectric pattern on the lowermost second dielectric pattern was not found in prior art. Claim 11 is objected to since it depends from claim 10.
The limitations of claim 14 including: wherein, on a boundary between the cell array region and the connection region, one of the second dielectric patterns is horizontally in contact with one of the third dielectric patterns was not found in prior art. Claims 15-17 are objected to since the claims depends from claim 14.
Conclusion
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813