DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 7, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on June 18, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 12, 13, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "the first substrate comprises: …; wherein an upper pad …", as recited in claims 1 and 19, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: (i.e. Fig. 2 and [0023]: 100 excludes 141 and 142). See MPEP §2173.03.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 7, 8, 12, 13, 19 and 20, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2022/0139880) in view of Choi et al. (2022/0157702).
Lee et al. show in Fig. 9 and related text:
As for claim 1, a semiconductor package 1000H comprising:
a lower package 340/310/321/200/100/330; and
an upper package 500 on the lower package, wherein the lower package comprises:
a first substrate 330;
a plurality of chip stacks 100/200 on the first substrate;
a first mold structure 310 on the first substrate and covering at least a portion of the plurality of chip stacks; and
a second substrate 340 on the first mold structure,
wherein the plurality of chip stacks comprise:
a first semiconductor chip 100; and
a second semiconductor chip 200 on the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first semiconductor substrate 111;
a first wiring layer 131/132 adjacent the first semiconductor substrate, wherein the first wiring layer comprises a plurality of wiring patterns (upper portion of) 132;
a first circuit layer 121/122 (except the one directly contacts 141)/ID1 on the first semiconductor substrate, wherein the first circuit layer comprises a transistor ID1 and a plurality of circuit wirings 122 connected to the transistor; and
a chip through electrode 141/142 penetrating at least a portion of the first circuit layer and penetrating at least a portion of the first semiconductor substrate,
wherein the first substrate comprises:
a plurality of insulating layers 331; and
a plurality of redistribution patterns 332 in the plurality of insulating layers;
wherein a width of the first semiconductor chip is equal to a width of the second semiconductor chip (claim 19), and
wherein the chip through electrode is connected to the plurality of wiring patterns and the plurality of circuit wirings.
As for claims 19 and 20, a semiconductor package 1000H comprising:
a first substrate 330;
a plurality of chip stacks 100/200 on the first substrate;
a conductive post 321 on the first substrate and spaced apart from the plurality of chip stacks in a first direction X;
a mold structure 310 covering the conductive post and the plurality of chip stacks; and
a second substrate 340 on the mold structure,
wherein the plurality of chip stacks comprise a first semiconductor chip 100 and a second semiconductor chip 200 on the first semiconductor chip,
wherein the first semiconductor chip comprises:
a wiring layer 131/132;
a circuit layer 121/122 (except the one directly contacts 141)/ID1 on the wiring layer;
a semiconductor substrate 111 interposed between the wiring layer and the circuit layer; and
a chip through electrode 141/142 penetrating the semiconductor substrate,
wherein the wiring layer comprises:
a wiring insulating layer 131; and
a plurality of wiring patterns 132 in the wiring insulating layer,
wherein the circuit layer comprises:
a first circuit insulating layer (lower portion of) 121;
a plurality of transistors ID1 in the first circuit insulating layer;
a second circuit insulating layer (upper portion of) 121 on the first circuit insulating layer;
a plurality of first circuit wirings 122 in the second circuit insulating layer; and
a power pad (one directly contacts 141 of) 122 on a lower surface of the second circuit insulating layer,
wherein the first substrate comprises:
a plurality of insulating layers 331; and
a plurality of redistribution patterns 332 in the plurality of insulating layers;
wherein the power pad contacts the chip through electrode,
wherein the chip through electrode penetrates the first circuit insulating layer,
wherein the chip through electrode has a first height,
wherein a vertical height from an upper surface of the first circuit insulating layer to an upper surface of the wiring insulating layer is a second height; and
wherein the first height is greater than or equal to the second height.
Lee et al. do not disclose a height of the chip through electrode ranges from 2 µm to 50 µm (claim 1); an upper pad on an uppermost one of the plurality of redistribution patterns; a top surface of the upper pad is at a level higher than a top surface of an uppermost one of the plurality of insulating layers (claims 1 and 19); the first height has a range of 2 µm to 50 µm (claim 19) and the second height has a range of 2 µm to 50 µm (claim 20).
Choi et al. teach in Fig. 1 and related text an upper pad 130 on an uppermost one of the plurality of redistribution patterns120;
a top surface of the upper pad is at a level higher than a top surface of an uppermost one 105 of the plurality of insulating layers 101/102/103/104/105.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include an upper pad on an uppermost one of the plurality of redistribution patterns; a top surface of the upper pad being at a level higher than a top surface of an uppermost one of the plurality of insulating layers, as taught by Choi et al., a height of the chip through electrode ranging from 2 µm to 50 µm; the first height having a range of 2 µm to 50 µm; and the second height having a range of 2 µm to 50 µm, in Lee et al.’s device, in order to increase yield, reduce vertical contact electromigration resistance and optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
As for claim 2, the combined device shows the chip through electrode extends into an upper portion of the first wiring layer, and
wherein the chip through electrode is in direct contact with an uppermost one of the plurality of wiring patterns (Lee: Fig. 9).
As for claim 3, the combined device shows the first circuit layer further comprises a power pad (one directly contacts 141 of) 122 on the chip through electrode in the first circuit layer,
wherein the power pad is connected to the chip through electrode and the plurality of circuit wirings (Lee: Fig. 9).
As for claim 4, the combined device shows the first circuit layer comprises:
a first circuit insulating layer (lower portion of) 121 covering the transistor;
a circuit plug penetrating the first circuit insulating layer and connected to the transistor;
a second circuit insulating layer (upper portion of) 121 on the first circuit insulating layer and covering the plurality of circuit wirings;
a circuit upper pad 122 on an upper surface of the second circuit insulating layer; and
a circuit lower pad 122 on a lower surface of the second circuit insulating layer,
wherein the circuit lower pad is in contact with the circuit plug (Lee: Fig. 9).
As for claim 5, the combined device shows the first substrate comprises an under bump pattern 332 on a lower surface of the first substrate and an external connection terminal 41 on a lower surface of the under bump pattern,
wherein the external connection terminal is connected to the plurality of chip stacks through the under bump pattern (Lee: Fig. 9).
As for claim 7, the combined device shows the first wiring layer further comprises a wiring pad (lower portion of) 132 on a lower surface of the first wiring layer,
wherein the lower package further comprises a connection terminal 42 interposed between the plurality of chip stacks and the upper pad, and
wherein the connection terminal is in contact with the wiring pad and the upper pad (Lee: Fig. 9).
As for claim 8, the combined device shows the lower package is provided on the first substrate and further comprises a conductive post 321 spaced apart from the plurality of chip stacks in a first direction X, and
wherein the conductive post contacts the upper pad (Lee: Fig. 9).
As for claim 12, the combined device shows a side surface of the first semiconductor chip and a side surface of the second semiconductor chip are aligned parallel to each other (Lee: Fig. 9).
As for claim 13, the combined device shows a side surface of the first semiconductor chip and a side surface of the second semiconductor chip are in contact with a first mold structure 310 (Lee: Fig. 9).
Claim(s) 6, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2022/0139880) and Choi et al. (2022/0157702) in view of An et al. (2014/0162449).
Lee et al. and Choi et al. show the first circuit layer further comprises a circuit upper pad 122 on an upper surface of the first circuit layer,
wherein the second semiconductor chip comprises:
a second semiconductor substrate 211;
a second wiring layer 231/232 adjacent the second semiconductor substrate; and
a second circuit layer 221/ID2/222 on the second semiconductor substrate,
wherein the second wiring layer comprises a wiring pad 222 on a lower surface of the second wiring layer (Lee: Fig. 9).
Lee et al. and Choi et al. do not disclose the plurality of chip stacks further comprise a connection terminal between the first semiconductor chip and the second semiconductor chip, and wherein the connection terminal is in contact with the circuit upper pad and the wiring pad.
An et al. teach in Fig. 14 and related text the plurality of chip stacks 403 further comprise a connection terminal 75 between the first semiconductor chip 100a and the second semiconductor chip 100b, and
wherein the connection terminal is in contact with the circuit upper pad 63 (of 100a) and the wiring pad 63 (of 100b).
Lee et al., Choi et al. and An et al. are analogous art because they are directed to a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. and Choi et al. with the specified feature(s) of An et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a connection terminal between the first semiconductor chip and the second semiconductor chip, and wherein the connection terminal being in contact with the circuit upper pad and the wiring pad, as taught by An et al., in Lee et al. and Choi et al.'s device, in order to provide better density, lower cost, better electrical performance and enhance system speed.
Claim(s) 9, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2022/0139880) and Choi et al. (2022/0157702) in view of Kuo et al. (2017/0084589).
Lee et al. and Choi et al. show the upper package comprises:
a third semiconductor chip 500 on the second substrate (Lee: [0068]).
Lee et al. and Choi et al. do not disclose the upper package comprises a package substrate interposed between the second substrate and the third semiconductor chip; and a second mold structure covering at least a portion of an upper surface of the package substrate and the third semiconductor chip.
Kuo et al. teach in Fig. 5 and related text the upper package 2000 comprises:
a package substrate 2200 interposed between the second substrate 600/650 and the third semiconductor chip 2300 (or 2400); and
a second mold structure 2600 covering at least a portion of an upper surface of the package substrate and the third semiconductor chip.
Lee et al., Choi et al. and Kuo et al. are analogous art because they are directed to a semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. and Choi et al. with the specified feature(s) of Kuo et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a package substrate interposed between the second substrate and the third semiconductor chip and a second mold structure covering at least a portion of an upper surface of the package substrate and the third semiconductor chip, as taught by Kuo et al., in Lee et al. and Choi et al.’s device, in order to improve power delivery, improve reliability and durability of the device; to protect the device and reduce the influence from the outside environment.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9, 12, 13, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MEIYA LI/Primary Examiner, Art Unit 2811
Prosecution Insights