DETAILED ACTIO N Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species A claims 1-20 in the reply filed on 02/27/26 is acknowledged. Foreign Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. FILLIN "Insert series code and serial no. of parent." JP2021-073300 , filed on FILLIN "Enter the date filing of the parent application." 04/23/2021 . Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/18/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1 , 3 , 4 - 6 , 8, 10-11, 13, 15-16, 18, and 20 are rejected under U.S.C. 103 as being unpatentable over Kurokawa et al.; US 2019/0172773 A1; 12/2018 in view of Nakajima et al.; US 2010/0109052 A1; 10/2009 . Claim 1: Kurokawa discloses a semiconductor device comprising: a semiconductor substrate ( Fig. 2 substrate 30 ); at least one first transistor ( Fig. 2 unit transistor 60 ) on the semiconductor substrate ( Fig. 2 #30 ), each first transistor including a mesa structure ( Fig. 2 mesa layers 35 ) including one or more semiconductor layers ( [0059] The emitter mesa layers 35 are each formed in a double-layer structure constituted by a high-concentration n-type GaAs layer having a thickness of about 100 nm and a high-concentration n-type InGaAs layer having a thickness of about 100 nm ); a wiring layer ( Fig. 2 emitter electrode E0 ) covering the mesa structure ( Fig. 2 #35 ); a first bump ( Fig. 2: pillar bump (metal member) 40 ) overlapping the at least one first transistor ( Fig. 2 #60 ) and electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ), the first bump ( Fig. 2 #40 ) extending in a first direction parallel to the semiconductor substrate ( extending in the x direction as shown in Fig. 2 ); a first distance between the first side ( left side of Fig. 3 #40 ) and the first end portion of the mesa structure ( left side of Fig. 3 #35 ) in the second direction ( y-direction as shown in Fig. 3 ) is greater than a second distance between the second side ( right side of Fig. 3 #40 ) and the second end portion of the mesa structure ( right side of Fig. 3 #35 ) in the second direction ( y-direction as shown in Fig. 3 ). Kurokawa does not appear to disclose a second bump extending in the first direction and facing the first bump in a second direction orthogonal to the first direction, wherein the mesa structure includes a first end portion at one end in the second direction and a second end portion at another end in the second direction, the first end portion being closer to the second bump than the second end portion in the second direction, in plan view in a direction perpendicular to the semiconductor substrate, an outer periphery of the first bump includes a first side and a second side extending in the first direction and next to each other in the second direction, the first side being closer to the second bump than the second side in the second direction, the first end portion and the second end portion of the mesa structure being between the first side and the second side, and in plan view in the direction perpendicular to the semiconductor substrate. However, Nakajima teaches a second bump ( Fig. 64 top left group with left #419b ) extending in the first direction ( as shown in Fig. 64 ) and facing the first bump ( Fig. 64 first bump on right side of left group facing the second bump ) in a second direction orthogonal to the first direction ( as shown in Fig. 64 ), wherein the mesa structure ( Fig. 63 base mesa 433 ) includes a first end portion at one end in the second direction ( top view in Fig. 64 right side of 433 ) and a second end portion at another end in the second direction ( top view in Fig. 64 left side of 433 ), the first end portion being closer to the second bump ( right side of Fig. 64 top left group with second bump as the right #419b area ) than the second end portion in the second direction ( as shown in Fig. 64 ), in plan view in a direction perpendicular to the semiconductor substrate ( Fig. 63 substrate 430 ), an outer periphery of the first bump ( Fig. 64 top left group with left #419b ) includes a first side ( Fig. 64 right side of top left group with left #419b ) and a second side ( Fig. 64 left side of top left group with right #419b ) extending in the first direction ( extending in the first direction as shown in Fig. 64 ) and next to each other in the second direction ( beside each other as shown in Fig. 64 ), the first side being closer to the second bump ( Fig. 64 top left group with right #419b ) than the second side in the second direction ( as shown in Fig. 64 first side is close to the second bump in the second direction ), the first end portion ( Fig. 63 right side of 433 ) and the second end portion ( Fig. 63 left side of 433 ) of the mesa structure ( Fig. 63 #433 ) being between the first side and the second side ( as shown in Figs. 63 and 64 ), and in plan view in the direction perpendicular to the semiconductor substrate ( Fig. 63 #430 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement a second bump extending in the first direction and facing the first bump in a second direction orthogonal to the first direction, wherein the mesa structure includes a first end portion at one end in the second direction and a second end portion at another end in the second direction, the first end portion being closer to the second bump than the second end portion in the second direction, in plan view in a direction perpendicular to the semiconductor substrate, an outer periphery of the first bump includes a first side and a second side extending in the first direction and next to each other in the second direction, the first side being closer to the second bump than the second side in the second direction, the first end portion and the second end portion of the mesa structure being between the first side and the second side, and in plan view in the direction perpendicular to the semiconductor substrate because this allows for improved mechanical reliability, enhanced thermal management, and prevents solder bridging in dense layouts. Claim 3: Kurokawa discloses a semiconductor device comprising: a semiconductor substrate ( Fig. 2 substrate 30 ); at least one first transistor ( Fig. 2 unit transistor 60 ) on the semiconductor substrate ( Fig. 2 #30 ), each first transistor including a mesa structure ( Fig. 2 mesa layers 35 ) including one or more semiconductor layers ( [0059] The emitter mesa layers 35 are each formed in a double-layer structure constituted by a high-concentration n-type GaAs layer having a thickness of about 100 nm and a high-concentration n-type InGaAs layer having a thickness of about 100 nm ); a wiring layer ( Fig. 2 emitter electrode E0 ) covering the mesa structure ( Fig. 2 #35 ); a first bump ( Fig. 2: pillar bump (metal member) 40 ) overlapping the at least one first transistor ( Fig. 2 #60 ) and electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ), the first bump ( Fig. 2 #40 ) extending in a first direction parallel to the semiconductor substrate ( extending in the x direction as shown in Fig. 2 ); a first distance between the first side ( left side of Fig. 3 #40 ) and the first end portion of the mesa structure ( left side of Fig. 3 #35 ) in the second direction ( y- direction as shown in Fig. 3 ) is greater than a second distance between the second side ( right side of Fig. 3 #40 ) and the second end portion of the mesa structure ( right side of Fig. 3 #35 ) in the second direction ( y-direction as shown in Fig. 3 ). Kurokawa does not appear to disclose a second bump on a side of a geometric center of the semiconductor substrate opposite to a side on which the first bump is, wherein the mesa structure includes a first end portion at one end in a second direction orthogonal to the first direction and a second end portion at another end in the second direction, the first end portion being closer to the geometric center of the semiconductor substrate than the second end portion in the second direction, in plan view in a direction perpendicular to the semiconductor substrate, an outer periphery of the first bump includes a first side and a second side extending in the first direction and arranged next to each other in the second direction, the first side being closer to the geometric center of the semiconductor substrate than the second side in the second direction, the first end portion and the second end portion of the mesa structure being between the first side and the second side, and in plan view in the direction perpendicular to the semiconductor substrate . However, Nakajima teaches a second bump ( Fig. 64 top right group with left #419b ) on a side of a geometric center of the semiconductor substrate ( as shown in Fig. 64 ) opposite to a side on which the first bump is ( Fig. 64 first bump is opposite second bump ), wherein the mesa structure ( Fig. 63 base mesa 433 ) includes a first end portion at one end in a second direction orthogonal to the first direction ( top view in Fig. 64 right side of Fig. 63 #433 ) and a second end portion at another end in the second direction ( top view in Fig. 64 left side of Fig. 63 #433 ), the first end portion being closer to the geometric center ( as shown in Fig. 64 ) of the semiconductor substrate ( Fig. 63 #430 ) than the second end portion in the second direction ( as shown in Fig. 64 ), in plan view in a direction perpendicular to the semiconductor substrate ( Fig. 63 substrate 430 ), an outer periphery of the first bump ( Fig. 64 top left group with left #419b ) includes a first side ( Fig. 64 right side of top left group with left #419b ) and a second side ( Fig. 64 left side of top left group with right #419b ) extending in the first direction ( extending in the first direction as shown in Fig. 64 ) and arranged next to each other in the second direction ( beside each other as shown in Fig. 64 ), the first side being closer to the geometric center of the semiconductor substrate than the second side in the second direction, the first end portion ( Fig. 63 right side of 433 ) and the second end portion ( Fig. 63 left side of 433 ) of the mesa structure ( Fig. 63 #433 ) being between the first side and the second side ( as shown in Figs. 63 and 64 ), and in plan view in the direction perpendicular to the semiconductor substrate ( Fig. 63 #430 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement a second bump on a side of a geometric center of the semiconductor substrate opposite to a side on which the first bump is, wherein the mesa structure includes a first end portion at one end in a second direction orthogonal to the first direction and a second end portion at another end in the second direction, the first end portion being closer to the geometric center of the semiconductor substrate than the second end portion in the second direction, in plan view in a direction perpendicular to the semiconductor substrate, an outer periphery of the first bump includes a first side and a second side extending in the first direction and arranged next to each other in the second direction, the first side being closer to the geometric center of the semiconductor substrate than the second side in the second direction, the first end portion and the second end portion of the mesa structure being between the first side and the second side, and in plan view in the direction perpendicular to the semiconductor substrate because this facilitates symmetrical electrical connectivity and balanced mechanical stress. Claim 4: Kurokawa and Nakajima disclose the semiconductor device according to Claim 1 ( as discussed above ). Kurokawa teaches a collector layer ( Fig. 2: collector layer 32 ) on the semiconductor substrate ( Fig. 2 #30 ); a base layer ( Fig. 2: base layer 33 ) on the collector layer ( Fig. 2 #32 ); and an emitter layer ( Fig. 2: emitter layer 34 ) on the base layer ( Fig. 2 #33 ), wherein the mesa structure ( [0058] Multiple mesas are formed on the sub-collector layer 31. Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other ) includes at least a portion of the collector layer ( Fig. 2 #32 ) and the base layer ( Fig. 2 #33 ). Claim 5: Kurokawa and Nakajima disclose the semiconductor device according to Claim 1 ( as discussed above ). Kurokawa teaches an insulating film ( Fig. 2 insulating film 50 ) covering the wiring layer ( [0064] The first-layer emitter wiring E1 is electrically connected to the emitter electrodes E0 via cavities formed in the first-layer insulating film 50 ) and having an opening ( Fig. 2 plural of cavities 45 ) in a region overlapping ( as shown in Fig. 2 ) at least the mesa structure ( Fig. 2 #35 ), wherein the first bump ( Fig. 2 #40 ) is electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ) through the opening ( Fig. 2 #45 ) , and the insulating film ( Fig. 2 #50 ) is an inorganic protective film including an inorganic material ( [0063] A single SiN film or a multilayer film of a SiN film and a resin film, for example, is used for the first-layer insulating film 50 ) . Claim 6: Kurokawa and Nakajima disclose the semiconductor device according to Claim 1 ( as discussed above). Kurokawa does not appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because this optimizes high-power semiconductor performance by enabling vertical current flow, reducing parasitic capacitance, and providing direct thermal management. Claim 8: Kurokawa and Nakajima disclose The semiconductor device according to Claim 3 ( as discussed above). Kurokawa teaches a collector layer ( Fig. 2: collector layer 32 ) on the semiconductor substrate ( Fig. 2 #30 ); a base layer ( Fig. 2: base layer 33 ) on the collector layer ( Fig. 2 #32 ); and an emitter layer ( Fig. 2: emitter layer 34 ) on the base layer ( Fig. 2 #33 ), wherein the mesa structure ( [0058] Multiple mesas are formed on the sub-collector layer 31. Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other ) includes at least a portion of the collector layer ( Fig. 2 #32 ) and the base layer ( Fig. 2 #33 ). Claim 10: Kurokawa and Nakajima disclose the semiconductor device according to Claim 3 ( as discussed above). Kurokawa teaches an insulating film ( Fig. 2 insulating film 50 ) covering the wiring layer ( [0064] The first-layer emitter wiring E1 is electrically connected to the emitter electrodes E0 via cavities formed in the first-layer insulating film 50 ) and having an opening ( Fig. 2 plural of cavities 45 ) in a region overlapping ( as shown in Fig. 2 ) at least the mesa structure ( Fig. 2 #35 ), wherein the first bump ( Fig. 2 #40 ) is electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ) through the opening ( Fig. 2 #45 ) , and the insulating film ( Fig. 2 #50 ) is an inorganic protective film including an inorganic material ( [0063] A single SiN film or a multilayer film of a SiN film and a resin film, for example, is used for the first-layer insulating film 50 ) . Claim 11: Kurokawa and Nakajima disclose the semiconductor device according to Claim 4 ( as discussed above). Kurokawa teaches an insulating film ( Fig. 2 insulating film 50 ) covering the wiring layer ( [0064] The first-layer emitter wiring E1 is electrically connected to the emitter electrodes E0 via cavities formed in the first-layer insulating film 50 ) and having an opening ( Fig. 2 plural of cavities 45 ) in a region overlapping ( as shown in Fig. 2 ) at least the mesa structure ( Fig. 2 #35 ), wherein the first bump ( Fig. 2 #40 ) is electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ) through the opening ( Fig. 2 #45 ) , and the insulating film ( Fig. 2 #50 ) is an inorganic protective film including an inorganic material ( [0063] A single SiN film or a multilayer film of a SiN film and a resin film, for example, is used for the first-layer insulating film 50 ) . Claim 13: Kurokawa and Nakajima disclose the semiconductor device according to Claim 8 ( as discussed above). Kurokawa teaches an insulating film ( Fig. 2 insulating film 50 ) covering the wiring layer ( [0064] The first-layer emitter wiring E1 is electrically connected to the emitter electrodes E0 via cavities formed in the first-layer insulating film 50 ) and having an opening ( Fig. 2 plural of cavities 45 ) in a region overlapping ( as shown in Fig. 2 ) at least the mesa structure ( Fig. 2 #35 ), wherein the first bump ( Fig. 2 #40 ) is electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ) through the opening ( Fig. 2 #45 ) , and the insulating film ( Fig. 2 #50 ) is an inorganic protective film including an inorganic material ( [0063] A single SiN film or a multilayer film of a SiN film and a resin film, for example, is used for the first-layer insulating film 50 ) . Claim 15: Kurokawa and Nakajima disclose the semiconductor device according to Claim 3 ( as discussed above). Kurokawa does not appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because this enhances thermal management, increase integration density, and reduce parasitic resistance. Claim 16: Kurokawa and Nakajima disclose the semiconductor device according to Claim 4 ( as discussed above ). Kurokawa does not appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because the second bump is designed to provide high-efficiency power handling, improved thermal dissipation, and efficient isolation. Claim 18: Kurokawa and Nakajima disclose the semiconductor device according to claim 8 ( as discussed above). Kurokawa does not appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because this maximizes vertical space efficiency, reduces parasitic resistance and inductance, and improves thermal management. Claim 20: Kurokawa and Nakajima disclose the semiconductor device according to claim 10 ( as discussed above). Kurokawa does not appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nakajima with Kurokawa to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because the second bump provides high-efficiency power handling, improved thermal dissipation, and efficient isolation. Claim 2 is rejected under U.S.C. 103 as being unpatentable over Kurokawa et al.; US 2019/0172773 A1; 12/2018 in view of Nakajima et al.; US 2010/0109052 A1; 10/2009 as it relates to claim 1 above and further in view of Ishikawa et al.; US 11,289,415 B2; 09/2019; 09/2019 Claim 2: Kurokawa and Nakajima disclose the semiconductor device according to Claim 1 ( as discussed above). Neither Kurokawa nor Nakajima appear to disclose one of end portions of the semiconductor substrate in the second direction is closer to the first bump than to the second bump, and a distance between the one of the end portions and the first side is greater than a distance between the one of the end portions and the second side. However, Ishikawa teaches one of end portions ( Fig. 1B top side of mounting substrate 40 ) of the semiconductor substrate ( Fig. 1B #40 ) in the second direction ( Fig. 1B y-direction ) is closer to the first bump ( Fig. 1A first bump 21 ) than to the second bump ( Fig. 1A second bump 22 ), and a distance between the one of the end portions ( Fig. 1B top side of #40 ) and the first side ( Fig. 1A bottom portion of 21 ) is greater than a distance between the one of the end portions ( Fig. 1B top side of #40 ) and the second side ( Fig. 1A top portion of 21 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ishikawa with Kurokawa and Nakajima to implement one of end portions of the semiconductor substrate in the second direction is closer to the first bump than to the second bump, and a distance between the one of the end portions and the first side is greater than a distance between the one of the end portions and the second side because this optimizes space for specialized, non-uniform, or sacrificial features while ensuring mechanical stability and electrical testing capability. Claim 7: Kurokawa , Nakajima, and Ishikawa disclose the semiconductor device according to Claim 2 ( as discussed above ). Kurokawa teaches a collector layer ( Fig. 2: collector layer 32 ) on the semiconductor substrate ( Fig. 2 #30 ); a base layer ( Fig. 2: base layer 33 ) on the collector layer ( Fig. 2 #32 ); and an emitter layer ( Fig. 2: emitter layer 34 ) on the base layer ( Fig. 2 #33 ), wherein the mesa structure ( [0058] Multiple mesas are formed on the sub-collector layer 31. Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other ) includes at least a portion of the collector layer ( Fig. 2 #32 ) and the base layer ( Fig. 2 #33 ). Claim 9: Kurokawa , Nakajima, and Ishikawa disclose the semiconductor device according to Claim 2 ( as discussed above ). Kurokawa teaches an insulating film ( Fig. 2 insulating film 50 ) covering the wiring layer ( [0064] The first-layer emitter wiring E1 is electrically connected to the emitter electrodes E0 via cavities formed in the first-layer insulating film 50 ) and having an opening ( Fig. 2 plural of cavities 45 ) in a region overlapping ( as shown in Fig. 2 ) at least the mesa structure ( Fig. 2 #35 ), wherein the first bump ( Fig. 2 #40 ) is electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ) through the opening ( Fig. 2 #45 ) , and the insulating film ( Fig. 2 #50 ) is an inorganic protective film including an inorganic material ( [0063] A single SiN film or a multilayer film of a SiN film and a resin film, for example, is used for the first-layer insulating film 50 ) . Claim 12: Kurokawa , Nakajima, and Ishikawa disclose the semiconductor device according to Claim 7 ( as discussed above ). Kurokawa teaches an insulating film ( Fig. 2 insulating film 50 ) covering the wiring layer ( [0064] The first-layer emitter wiring E1 is electrically connected to the emitter electrodes E0 via cavities formed in the first-layer insulating film 50 ) and having an opening ( Fig. 2 plural of cavities 45 ) in a region overlapping ( as shown in Fig. 2 ) at least the mesa structure ( Fig. 2 #35 ), wherein the first bump ( Fig. 2 #40 ) is electrically connected to the wiring layer ( [0067] The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via the cavities 45 ) through the opening ( Fig. 2 #45 ) , and the insulating film ( Fig. 2 #50 ) is an inorganic protective film including an inorganic material ( [0063] A single SiN film or a multilayer film of a SiN film and a resin film, for example, is used for the first-layer insulating film 50 ) . Claim 14: Kurokawa , Nakajima, and Ishikawa disclose the semiconductor device according to claim 2 ( as discussed above ). Neither Kurokawa nor Ishikawa appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ishikawa with Kurokawa and Nakajima to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transisto r because this will improve thermal management and parasitic reduction in power devices. Claim 17: Kurokawa , Nakajima, and Ishikawa disclose the semiconductor device according to Claim 7 ( as discussed above ). Neither Kurokawa nor Ishikawa appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ishikawa with Kurokawa and Nakajima to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because this will optimized heat dissipation, minimize parasitic resistance/inductance for high-frequency or power operations, and improve mechanical reliability. Claim 19: Kurokawa , Nakajima, and Ishikawa disclose the semiconductor device according to claim 9 ( as discussed above ). Neither Kurokawa nor Ishikawa appear to disclose at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor. However, Nakajima teaches at least one second transistor ( Fig. 63 emitter bump electrode 419b, collector bump electrode 419a, and base bump electrode 419c ) on the semiconductor substrate ( Fig. 63 #430 ), each second transistor ( as discussed above ) including a mesa structure ( Fig. 63 base mesa 433 ) including one or more semiconductor layers ( Fig .63 #436 and #434 ), wherein the second bump ( Fig. 64 right group right side bump) overlaps the at least one second transistor ( as shown in Fig. 63 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ishikawa with Kurokawa and Nakajima to implement at least one second transistor on the semiconductor substrate, each second transistor including a mesa structure including one or more semiconductor layers, wherein the second bump overlaps the at least one second transistor because this will improve thermal management and parasitic reduction in power devices. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KIMBERLY N FREY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5068 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 7:30 am - 5 pm . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.N.F./ Examiner, Art Unit 2817 /MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817