DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A, in the reply filed on 26 March 2026 is acknowledged. The traversal is on the grounds that examination of the full set of claims is more efficient than separate examination of each invention group and would require minimal additional search and not impose serious additional burden. This is not found persuasive because as indicated in the restriction requirement, the species require different fields of search, wherein lateral double-diffused metal-oxide semiconductor (LDMOS) field effect transistors, from which Species A is drawn to, are classified in at least CPC H10D 30/65 and vertical double-diffused metal-oxide semiconductor (VDMOS) field effect transistors, from which Species B is drawn to, are classified in at least CPC H10D 30/66, therefore requiring at least different classification searches and different search strategies, therefore imposing a serious additional search burden which would result in a less efficient examination.
The requirement is still deemed proper and is therefore made FINAL.
Claims 25-31 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species (B), there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 26 March 2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 18 October 2023 and 2 July 2025 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 8-9, 11-12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”) in view of Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”).
Regarding Claim 1, Giuliano teaches an apparatus comprising:
an integrated circuit package including (Fig. 61, para [0297] describes a package including numerous low gain stages 12A in series):
a first integrated circuit die (12A, Fig. 115, para [0379] describes forming a switching network 12A, such as the one depicted in Fig. 115, of the low gain stages on a single die) electrically coupled to a substrate (Fig. 123, para [0413] describes electrically coupling a die, such as used to form first integrated circuit die 12A, to a substrate);
wherein the first integrated circuit die (12A, Fig. 115) includes a plurality of first switches (52A and 52B, Fig. 115, para [0373] describes a circuit comprising the first switching network 12A of the first integrated circuit die further comprising a first plurality of stack switches 52A and 52B) and a plurality of second switches (54A and 54B, Fig. 115, para [0373] describes a circuit comprising the first switching network 12A of the first integrated circuit die further comprising a second plurality of phase switches 54A and 54B);
wherein the plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit (50A, Fig. 115, para [0371] describes a plurality of first charge transfer capacitors 50A interconnecting the first switches 52A and 52B with the second switches 54A and 54B), wherein the first switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches (this limitation “configured to” is a recitation of a property of the device; because the structure of the prior art, comprising a plurality of first switches (52A and 52B) and a plurality of second switches (54A and 54B) interconnected with a plurality of first capacitors (50A) to form a first switched capacitor circuit, is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))); and
a second integrated circuit die (51 and 59A, Fig. 115, para [0384] describes a phase controller 59A and stack controller 51 which may be comprised on a separate controller die together);
wherein the second integrated circuit die includes a controller circuit that is electrically coupled to control switching of the plurality of first switches and the plurality of second switches (51 and 59A, Fig. 115, para [0377] describes wherein the stack controller 51 and phase controller 59A of the second integrated circuit die are electrically coupled to the first plurality of switches 52A and 52B and second plurality of switches 54A and 54B, respectively, to control switching of the switches through control paths 55A and 55B); and
a third integrated circuit die (Fig. 61, para [0297] describes a package including numerous low gain stages 12A in series wherein a second switching network / low gain stage 12A of the N number of switching networks / low gain stages 12A would comprise a third integrated circuit die 12A such as shown in Fig. 115);
wherein the third integrated circuit die (12A, Fig. 115) includes a plurality of third switches (52A and 52B, Fig. 115, para [0373] describes a circuit comprising the switching network 12A of the third integrated circuit die wherein upon including a second switching network as shown in Fig. 61, the third integrated circuit die would further comprise a third plurality of stack switches 52A and 52B) and a plurality of fourth switches (54A and 54B, Fig. 115, para [0373] describes a circuit comprising the switching network 12A of the third integrated circuit die wherein upon including a second switching network as shown in Fig. 61, the third integrated circuit die would further comprising a fourth plurality of phase switches 54A and 54B);
wherein the plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit (50A, Fig. 115, para [0371] describes a plurality of charge transfer capacitors 50A wherein upon including a second switching network as shown in Fig. 61, the third integrated circuit die would further comprise a second plurality of capacitors 50A interconnecting the third switches 52A and 52B with the plurality of fourth switches 54A and 54B), wherein the second switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of third switches and the plurality of fourth switches (this limitation “configured to” is a recitation of a property of the device; because the structure of the prior art, comprising a plurality of third switches (52A and 52B) and a plurality of fourth switches (54A and 54B) interconnected with a plurality of second capacitors (50A) to form a second switched capacitor circuit, is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))); and
wherein the controller circuit is electrically coupled to control switching of the plurality of third switches and the plurality of fourth switches (51 and 59A, Fig. 115, para [0377] wherein upon adding a second switching network 12A to comprise the third integrated circuit die, the controller circuits 51 and 59A would further be electrically coupled to control switching of the plurality of third switches 52A and 52B and fourth switches 54A and 54B); and
wherein at least one of the plurality of first switches and the plurality of second switches has a different current rating than at least one of the plurality of third switches and the plurality of fourth switches (52A, 52B, 54A and 54B, Fig. 115, para [0380] describes wherein the stack switches 52A and 52B of the plurality of first switches and the third plurality of switches are manufactured to experience higher voltages or currents than the phase switches 54A and 54B of the plurality of second switches and the plurality of fourth switches resulting in at least one of the plurality of first switches having a different current rating than at least one of the plurality of fourth switches).
Giuliano fails to explicitly disclose wherein the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are co-packaged.
However, Giuliano discloses in Fig. 115 and Fig. 123 through Fig. 133 and para [0416] a package structure (82) including a stack-die (56) integrating dies such as used in the first and third integrated circuit dies (12A) and second integrated circuit die (51 and 59A) wherein packaging the first, second and third integrated circuit dies in such a manner would result in the first, second and third integrated circuit dies being co-packaged.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the integrated circuit dies of Giuliano with the co-packaging structure of Giuliano to further disclose an apparatus comprising a first integrated circuit die, a second integrated circuit die and a third integrated circuit die that are co-packaged in order to provide the advantage of enabling an integrated circuit device to connect integrated circuit dies in series in order to provide an apparatus with a large transformation ratio (Giuliano, para [0297]).
Giuliano further fails to disclose wherein the first integrated circuit die and the second integrated circuit die are electrically coupled to a lead frame.
However, Luo teaches a similar apparatus wherein the first integrated circuit die and the second integrated circuit die are electrically coupled to a lead frame (107, 108 and 106, Fig. 1A, column 4, lines 40-43 describes mounting circuit elements 102-108 to a Power Quad Flat No Lead Package leadframe wherein element 107 and 108 are a first and second semiconductor die and element 106 is a second semiconductor die).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano with Luo to further disclose an apparatus comprising a lead frame electrically coupled to a first integrated circuit die and a second integrated circuit die in order to provide the well-known advantage of enabling a semiconductor apparatus to have input and output pins connected to the apparatus enabling independent electrical communication to and from semiconductor dies on a lead frame.
Regarding Claim 3, the combination of Giuliano and Luo discloses the apparatus of claim 1, wherein the integrated circuit package is a surface-mounted package (Luo, Fig. 1A, column 4, lines 38-42 describe wherein the surface components included integrated circuit dies 106-108 may be mounted to the Power Quad Flat No Lead Package leadframe).
Regarding Claim 4, the combination of Giuliano and Luo discloses the apparatus of claim 3, wherein the integrated circuit package is a flat no-lead package (Luo, Fig. 1A, column 4, lines 38-42 describe wherein the surface components included integrated circuit dies 106-108 may be mounted to the Power Quad Flat No Lead Package leadframe).
Regarding Claim 5, the combination of Giuliano and Luo discloses the apparatus of claim 4, wherein the integrated circuit package is a quad flat no-lead package (Luo, Fig. 1A, column 4, lines 38-42 describe wherein the surface components included integrated circuit dies 106-108 may be mounted to the Power Quad Flat No Lead Package leadframe).
Regarding Claim 8, the combination of Giuliano and Luo discloses the apparatus of claim 1, wherein the controller circuit is configured to control switching of switches having a current rating of between about 10 amps and about 40 amps (Giuliano, 51 and 59A, Fig. 115, wherein this limitation “configured to” is a recitation of a property of the device; because the structure of the prior art, comprising a controller circuit (51 and 59A), is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))).
Regarding Claim 9, the combination of Giuliano and Luo discloses the apparatus of claim 1, wherein the first integrated circuit die includes a first replica switch (Giuliano, 12A, Fig. 62, para [0300] describes wherein the switching network 12A such as found in the first integrated circuit die may comprise a first set of first and second switches 1 and 2 on a left side of the switching network 12A and a second set of first and second switches 1 and 2 replicated on a right side of the switching network 12A), wherein at least two terminals of the first replica switch are electrically connected to at least two corresponding terminals of one switch of the plurality of first switches or the plurality of second switches (Giuliano, 12A, Fig. 62, para [0300] describes wherein first switches 1 of both the first switches and first replica switches are in a complementary state and can be seen sharing a same input terminal Vin and output terminal to a second switching network 12D).
Regarding Claim 11, the combination of Giuliano and Luo discloses the apparatus of claim 9, wherein the first replica switch is configured to sense a current flowing through the one switch to which its terminals are electrically connected (Giuliano, 1 and 12A, Fig. 62, wherein this limitation “configured to” is a recitation of a property of the device; because the structure of the prior art, comprising a first replica switch (1’s on the right side of switching network 12A), is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))).
Regarding Claim 12, the combination of Giuliano and Luo discloses the apparatus of claim 9, wherein the first replica switch is configured to detect a fault associated with the one switch to which its terminals are electrically connected (Giuliano, 1 and 12A, Fig. 62, wherein this limitation “configured to” is a recitation of a property of the device; because the structure of the prior art, comprising a first replica switch (1’s on the right side of switching network 12A), is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))).
Regarding Claim 17, the combination of Giuliano and Luo discloses the apparatus of claim 1, wherein the first integrated circuit die electrically coupled to the lead frame using wire-bonding (Luo, 107, Fig. 1A, column 4, lines 38-40 describe wire bonding elements 102-109 wherein elements 102-109 include a first integrated circuit die 107).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”) in view of Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”) in further view of Milind Bhagavat et al. (US 2020/0066677 A1; hereinafter “Bhagavat”).
Regarding Claim 2, the combination of Giuliano and Luo discloses all the limitations of claim 1.
Giuliano and Luo fail to explicitly disclose the apparatus of claim 1, wherein the first switched capacitor circuit has a power rating of about 100 Watts to about 1,000 Watts.
However, Bhagavat teaches a similar apparatus, wherein the first switched capacitor circuit has a power rating of about 100 Watts to about 1,000 Watts (302 and 304, Fig. 3, para [0025] describes integrated voltage regulator dies 302 and 304 which can sustain the introduction of 400 to 700 watts power to the integrated circuit package resulting in a first integrated circuit die comprising a first switched capacitor circuit such as described in para [0031] having a power rating of about 100 Watts to about 1,000 Watts).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano and Luo with Bhagavat to further disclose wherein a first switched capacitor circuit has a power rating of about 100 Watts to about 1,000 Watts in order to provide the advantage of providing power semiconductor dies which can sustain requirements for substantially large currents preventing undesirable device characteristics when large power ratings are introduced into the apparatus (Bhagavat, para [0025]).
Claims 6, 7, 18-19, 22 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”) in view of Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”) in further view of Mou-Shiung Lin et al. (US 2010/0165585 A1; hereinafter “Lin”).
Regarding Claim 6, the combination of Giuliano and Luo discloses all the limitations of claim 1.
Giuliano and Luo fail to explicitly disclose the apparatus of claim 1, wherein the controller circuit includes one or more complementary metal-oxide-semiconductor field effect transistors.
However, Lin teaches a similar apparatus wherein the controller circuit includes one or more complementary metal-oxide-semiconductor field effect transistors (1114a, Fig. 35, para [0260] describes wherein a switch controller circuit 1114a may comprise a P-type switching DMOS device 3115b and an N-type switching DMOS device 3115e resulting in a CMOS configuration).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano and Luo with Lin to substitute the transistor switching elements inside the controller circuit as described in para [0387] of Giuliano with the complementary P-type and N-type metal oxide field effect transistors of Lin for the predictable result of controlling switching elements inside a power device apparatus.
Regarding Claim 7, the combination of Giuliano and Luo discloses all the limitations of claim 1.
Giuliano and Luo fail to explicitly disclose the apparatus of claim 1, wherein the plurality of first switches and the plurality of second switches each include one or more double-diffused metal-oxide- semiconductor field effect transistors.
However, Lin teaches a similar apparatus wherein the plurality of first switches and the plurality of second switches each include one or more double-diffused metal-oxide-semiconductor field effect transistors (1114f, 1114h, 1114j, 1114g, 1114i and 1114k, Fig. 15, para [0167] describes wherein each switch MOS 1114f, 1114h, 1114j, 1114g, 1114i and 1114k of the apparatus as shown in Fig. 15 can be replaced with an LDMOS).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano and Luo with Lin to further disclose an apparatus wherein a plurality of first switches and a plurality of second switches each include one or more double-diffused metal-oxide-semiconductor field effect transistors in order to provide the advantage of minimizing voltage ripple of output by different on-off phases of switching MOS (Lin, para [0167]).
Regarding Claim 18, the combination of Giuliano and Luo discloses all the limitations of claim 1.
Giuliano and Luo fail to explicitly disclose the apparatus of claim 1, wherein the second integrated circuit die electrically coupled to the lead frame using flip-chip bonding.
However, Lin teaches a similar apparatus wherein the second integrated circuit die electrically coupled to the lead frame using flip-chip bonding (3210b, Fig. 33B and Fig. 35, para [0313] describes wherein a power management IC chip 3210b which comprises the controller circuit 1114a as described in para [0259], may be mounted by a flip-chip process wherein upon combining Lin with Giuliano and Luo, the second integrated circuit die comprising the controller circuit of Giuliano may be flip-chip mounted to the leadframe of Luo by the process as disclosed in Lin).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano and Luo with Lin to substitute the wire bonding of integrated circuit dies to a leadframe as disclosed by Luo with the flip-chip mounting process of Lin for the predictable result of securely mounting an integrated circuit die to a leadframe.
Regarding Claim 19, the combination of Giuliano and Luo discloses all the limitations of claim 1.
Giuliano and Luo fail to explicitly disclose the apparatus of claim 1, wherein the plurality of first switches and the plurality of second switches each include one or more lateral double-diffused metal- oxide semiconductor field effect transistors.
However, Lin teaches a similar apparatus wherein the plurality of first switches and the plurality of second switches each include one or more lateral double-diffused metal-oxide semiconductor field effect transistors (1114f, 1114h, 1114j, 1114g, 1114i and 1114k, Fig. 15, para [0167] describes wherein each switch MOS 1114f, 1114h, 1114j, 1114g, 1114i and 1114k of the apparatus as shown in Fig. 15 can be replaced with an LDMOS).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano and Luo with Lin to further disclose an apparatus wherein a plurality of first switches and a plurality of second switches each include one or more lateral double-diffused metal-oxide-semiconductor field effect transistors in order to provide the advantage of minimizing voltage ripple of output by different on-off phases of switching MOS (Lin, para [0167]).
Regarding Claim 22, the combination of Giuliano, Luo and Lin discloses the apparatus of claim 19, the apparatus further comprising:
a fourth integrated circuit die (Giuliano, 12A, Fig. 61, para [0297] describes a package including numerous low gain stages 12A in series wherein a third switching network / low gain stage 12A of the N number of switching networks / low gain stages 12A would comprise a fourth integrated circuit die 12A such as shown in Fig. 115) electrically coupled to the lead frame (Luo, 107, 108 and 106, Fig. 1A, column 4, lines 40-43 describes mounting circuit elements 102-108 to a Power Quad Flat No Lead Package leadframe wherein the fourth integrated circuit die of Giuliano would be mounted on the leadframe of Luo when combined);
wherein the fourth integrated circuit die (12A, Fig. 115) includes a plurality of fifth switches (52A and 52B, Fig. 115, para [0373] describes a circuit comprising the switching network 12A of the fourth integrated circuit die wherein upon including a third switching network as shown in Fig. 61, the fourth integrated circuit die would further comprise a plurality of fifth stack switches 52A and 52B) and a plurality of sixth switches (54A and 54B, Fig. 115, para [0373] describes a circuit comprising the switching network 12A of the fourth integrated circuit die wherein upon including a third switching network as shown in Fig. 61, the fourth integrated circuit die would further comprising a plurality of sixth phase switches 54A and 54B);
wherein the plurality of fifth switches and the plurality of sixth switches are interconnected with a plurality of third capacitors to form a third switched capacitor circuit (50A, Fig. 115, para [0371] describes a plurality of charge transfer capacitors 50A wherein upon including a third switching network as shown in Fig. 61, the fourth integrated circuit die would further comprise a third plurality of capacitors 50A interconnecting the fifth switches 52A and 52B with the plurality of sixth switches 54A and 54B), wherein the third switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of fifth switches and the plurality of sixth switches (this limitation “configured to” is a recitation of a property of the device; because the structure of the prior art, comprising a plurality of fifth switches (52A and 52B) and a plurality of sixth switches (54A and 54B) interconnected with a plurality of third capacitors (50A) to form a third switched capacitor circuit, is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))); and
wherein the controller circuit is electrically coupled to control switching of the plurality of fifth switches and the plurality of sixth switches (51 and 59A, Fig. 115, para [0377] wherein upon adding a third switching network 12A to comprise the fourth integrated circuit die, the controller circuits 51 and 59A would further be electrically coupled to control switching of the plurality of fifth switches 52A and 52B and sixth switches 54A and 54B).
The combination of Giuliano, Luo and Lin fails to explicitly disclose wherein the first integrated circuit die and the fourth integrated circuit die are vertically stacked.
However, Giuliano teaches in a further embodiment wherein the first integrated circuit die and the fourth integrated circuit die are vertically stacked (Fig. 95, para [0341] describes wherein any number of passive and active layers, wherein the active layers and passive layers would comprise the first and fourth integrated circuit dies including the switching network 12A, may be stacked on top of each other, resulting in the first integrated circuit die and fourth integrated circuit die being vertically stacked).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano, Luo and Lin with the further embodiment of Giuliano to further disclose an apparatus wherein any number of integrated circuit dies may be vertically stacked in order to provide the well-known advantage of enabling a power semiconductor apparatus to adjust the number of integrated circuit dies needed to meet the power demands of the apparatus.
Regarding Claim 32, the combination of Giuliano and Luo discloses all the limitations of claim 1.
Giuliano and Luo fail to explicitly disclose the apparatus of claim 1, wherein the plurality of first switches and the plurality of second switches are lateral double-diffused metal oxide semiconductor devices.
However, Lin teaches a similar apparatus wherein the plurality of first switches and the plurality of second switches are lateral double-diffused metal oxide semiconductor devices (1114f, 1114h, 1114j, 1114g, 1114i and 1114k, Fig. 15, para [0167] describes wherein each switch MOS 1114f, 1114h, 1114j, 1114g, 1114i and 1114k of the apparatus as shown in Fig. 15 can be replaced with an LDMOS).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Giuliano and Luo with Lin to further disclose an apparatus wherein the plurality of first switches and the plurality of second switches are lateral double-diffused metal oxide semiconductor devices in order to provide the advantage of minimizing voltage ripple of output by different on-off phases of switching MOS (Lin, para [0167]).
Allowable Subject Matter
Claims 10, 13-16, 20-21 and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 10, the prior art of record, David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”), Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”), Milind Bhagavat et al. (US 2020/0066677 A1; hereinafter “Bhagavat”) and Mou-Shiung Lin et al. (US 2010/0165585 A1; hereinafter “Lin”), either alone or in combination, fail to explicitly disclose wherein the first replica switch, as described by Giuliano in Fig. 62, is smaller in size than the one switch to which its terminals are electrically connected.
Regarding Claim 13, the prior art of record, David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”), Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”), Milind Bhagavat et al. (US 2020/0066677 A1; hereinafter “Bhagavat”) and Mou-Shiung Lin et al. (US 2010/0165585 A1; hereinafter “Lin”), either alone or in combination, fail to explicitly disclose wherein a second replica switch, as described by Giuliano in Fig. 62, and the another switch from the plurality of first switches and the plurality of second switches, are of different sizes; and wherein the first replica switch and the second replica switch are sized in proportion to the one switch and the another switch respectively.
Claims 14-16 are indicated as potentially allowable subject matter due to their dependence on claim 13 which has been objected to due to its dependence on rejected claim 1.
Regarding Claim 20, the prior art of record, David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”), Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”), Milind Bhagavat et al. (US 2020/0066677 A1; hereinafter “Bhagavat”) and Mou-Shiung Lin et al. (US 2010/0165585 A1; hereinafter “Lin”), either alone or in combination, fail to explicitly disclose wherein the first integrated circuit die (12A, Fig. 61 and Fig. 115 of Giuliano) includes a through-silicon via configured to form an electrical connection to either drain terminals or source terminals of either the plurality of first switches or the plurality of second switches.
Claim 21 is indicated as potentially allowable subject matter due to its dependence on claim 20 which has been objected to due to its dependence on rejected claim 19.
Regarding Claim 23, the prior art of record, David Giuliano (US 2017/0244318 A1; hereinafter “Giuliano”), Shiguo Luo et al (US 10802518 B1; hereinafter “Luo”), Milind Bhagavat et al. (US 2020/0066677 A1; hereinafter “Bhagavat”) and Mou-Shiung Lin et al. (US 2010/0165585 A1; hereinafter “Lin”), either alone or in combination, fail to explicitly disclose wherein the first integrated circuit die (12A, Fig. 61 and Fig. 115 of Giuliano) includes a plurality of metal clips coupled between at least two pairs of source and drain terminals of the plurality of first switches or the plurality of second switches.
Claim 24 is indicated as potentially allowable subject matter due to its dependence on claim 23 which has been objected to due to its dependence on rejected claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights