Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A (Vertical Double-Diffused MOSFET, drawn to claims 1-29) in the reply filed on 05/08/2026 is acknowledged. The traversal is on the ground(s) that “examination of the full set of claims 1-59 (encompassed by Species A and B) is more efficient than separate examination of each invention group and would require minimal additional search and not impose serious additional burden. Applicant submits that the designated groups identify shared subject matter relating to apparatuses and a method for power conversion. Applicant submits that the different species are not directed to mutually exclusive characteristics. Further in this regard, the apparatus of the designated species identify common features including a metal-oxide-semiconductor field effect transistor comprising a drift region, a source region, a drain region, and a gate.” This is not found persuasive because referring to the restriction requirement set forth in the previous office action, it clearly shows that the current flow direction stated by the examiner would be distinct for each of the two species. Vertical DMOS and LDMOS differ in current flow, drain location, voltage capability, current capability, on-resistance, chip area, integration, typical applications. There are also structural differences between VDMOS and LDMOS; in VDOMS source and gate are on the top surface, drain contact is on the backside of the substrate, current flows downward through an epitaxial drift region, and increasing voltage capability is mainly achieved by making the drift region thicker and more lightly doped, whereas in LDMOS source, gate and drain are all fabricated on the top surface, current travels horizontally beneath the gate and through a lateral drift region, and higher voltage is achieved by increasing the distance between the gate and drain which also increases on-resistance. When high power, high current and low conduction loss are required, VDMOS is chosen. When the transistor must be integrated with control circuitry on the same chip or when RF performance is important, LDMOS is chosen.
Additionally, it requires a different field of search; searching different classes/subclasses or electronic resources, or employing different search strategies or search queries, and the prior art applicable to one invention would not likely be applicable to another invention. The lateral double-diffused metal-oxide semiconductor (LDMOS) field effect transistors are classified in at least CPC H10D 30/65 and the vertical double-diffused metal-oxide semiconductor (VDMOS) field effect transistors are classified in at least CPC H10D 30/66, therefore requiring different classification searches and different search strategies.
Currently, claims 1-29 are pending, and claims 30-59 have been withdrawn from further consideration. The requirement is still deemed proper and is therefore made FINAL.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraph of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (Pub. No. US 2018/0082997 A1, herein Li).
Regarding claim 1, Li discloses an apparatus comprising: a vertical double-diffused metal-oxide-semiconductor field effect transistor 11 ([0001], [0020]) comprising a drift region 18 ([0024]), a source region 82/84/86, a drain region 16, and a gate 60 ([0035], [0038]); wherein the vertical double-diffused metal-oxide-semiconductor field effect transistor is isolated by an isolation trench 30-28/31 ([0028]) formed around the vertical double-diffused metal-oxide-semiconductor field effect transistor; wherein the isolation trench is filled with an electrically isolating material 31 ([0028]); and wherein the isolation trench goes through the bottom of the drain (Fig. 14).
Regarding claim 2, Li discloses the apparatus of claim 1, wherein the drift region is n- type ([0024]), the source region is p type ([0030]), the drain is n+ type ([0023]).
Regarding claim 3, Li discloses the apparatus of claim 1, wherein the electrically isolating material that fills the isolation trench is silicon ([0028]).
Regarding claim 4, Li discloses the apparatus of claim 1, wherein the electrically isolating material that fills the isolation trench is silicon dioxide ([0028]).
Regarding claim 5, Li discloses the apparatus of claim 1, wherein the isolation trench is formed using deep reactive ion etching ([0026]).
Regarding claim 7, Li discloses the apparatus of claim 1, wherein the isolation trench is formed using reactive ion beam etching ([0026]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (Pub. No. US 2018/0082997 A1, herein Li).
Regarding claims 6-10, Li does not specifically state the different etching methods claimed.
However, it is well-known in the art to have DRIE for deep and vertical trenches (high precision that is ideal for MEMS and TSVs), isotropic etching is best when uniform undercut is desired, RIBE is best for highly directional precise etching with chemical assistance, IBE is best for etching chemically inert materials using physical sputtering, IBAE combines physical and chemical mechanisms for improved performance (higher etch rates and better selectivity than ion milling with good profile control), and sputtering being a pure physical removal process generally slower and less selective than chemically assisted methods.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the method of Li by incorporating one of these alternative etching techniques, as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
Regarding claim 11, it would have been obvious to one of ordinary skill in the art to interchange the source and drain regions in a VDMOS device, as these terminal locations are a routine design choice dictated by the desired current flow direction and device layout because the overall operating principle and fabrication techniques remain substantially unchanged.
Claims 12, 14-17, 19-20 and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (Pub. No. US 2018/0082997 A1, herein Li) in view of Giuliano (Pub. No. US 2017/0244318 A1).
Regarding claims 12 and 26-27, as described above, Li discloses one or more of the vertical double-diffused metal-oxide semiconductor field effect transistors wherein the vertical double-diffused metal-oxide semiconductor field effect transistors are electrically isolated from each other by the isolation trenches. Li does not specifically show the remaining claimed limitations.
However, in the same field of endeavor, Giuliano teaches an apparatus comprising: an integrated circuit package including (Fig. 61, paragraph [0297] describes a package including numerous low gain stages 12A in series), a first integrated circuit die (12A, Fig. 115, paragraph [0379] describes forming a switching network 12A, such as the one depicted in Fig. 115, of the low gain stages on a single die) electrically coupled to a lead frame (Fig. 123, paragraph [0413] describes electrically coupling a die, such as used to form first integrated circuit die 12A, to a substrate); wherein the first integrated circuit die (12A, Fig. 115) includes a plurality of first switches (52A and 52B, Fig. 115, paragraph [0373] describes a circuit comprising the first switching network 12A of the first integrated circuit die further comprising a first plurality of stack switches 52A and 52B) and a plurality of second switches (54A and 54B, Fig. 115, paragraph [0373] describes a circuit comprising the first switching network 12A of the first integrated circuit die further comprising a second plurality of phase switches 54A and 54B); wherein the plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit (50A, Fig. 115, paragraph [0371] describes a plurality of first charge transfer capacitors 50A interconnecting the first switches 52A and 52B with the second switches 54A and 54B), wherein the first switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches (this limitation "configured to" is a recitation of a property of the device; because the structure of the prior art, comprising a plurality of first switches (52A and 52B) and a plurality of second switches (54A and 54B) interconnected with a plurality of first capacitors (50A) to form a first switched capacitor circuit, is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))); and a second integrated circuit die (51 and 59A, Fig. 115, paragraph [0384] describes a phase controller 59A and stack controller 51 which may be comprised on a separate controller die together); wherein the second integrated circuit die includes a controller circuit that is electrically coupled to control switching of the plurality of first switches and the plurality of second switches (51 and 59A, Fig. 115, paragraph [0377] describes wherein the stack controller 51 and phase controller 59A of the second integrated circuit die are electrically coupled to the first plurality of switches 52A and 52B and second plurality of switches 54A and 54B, respectively, to control switching of the switches through control paths 55A and 55B); and a third integrated circuit die (Fig. 61, paragraph [0297] describes a package including numerous low gain stages 12A in series wherein a second switching network / low gain stage 12A of the N number of switching networks / low gain stages 12A would comprise a third integrated circuit die 12A such as shown in Fig. 115); wherein the third integrated circuit die (12A, Fig. 115) includes a plurality of third switches (52A and 52B, Fig. 115, paragraph [0373] describes a circuit comprising the switching network 12A of the third integrated circuit die wherein upon including a second switching network as shown in Fig. 61, the third integrated circuit die would further comprise a third plurality of stack switches 52A and 52B) and a plurality of fourth switches (54A and 54B, Fig. 115, paragraph [0373] describes a circuit comprising the switching network 12A of the third integrated circuit die wherein upon including a second switching network as shown in Fig. 61, the third integrated circuit die would further comprising a fourth plurality of phase switches 54A and 54B); wherein the plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit (50A, Fig. 115, paragraph [0371] describes a plurality of charge transfer capacitors 50A wherein upon including a second switching network as shown in Fig. 61, the third integrated circuit die would further comprise a second plurality of capacitors 50A interconnecting the third switches 52A and 52B with the plurality of fourth switches 54A and 54B), wherein the second switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of third switches and the plurality of fourth switches (this limitation "configured to" is a recitation of a property of the device; because the structure of the prior art, comprising a plurality of third switches (52A and 52B) and a plurality of fourth switches (54A and 54B) interconnected with a plurality of second capacitors (50A) to form a second switched capacitor circuit, is substantially identical to the device claimed, the claims properties are presumed to be present (see MPEP 2112.01(I))); and wherein the controller circuit is electrically coupled to control switching of the plurality of third switches and the plurality of fourth switches (51 and 59A, Fig. 115, paragraph [0377] wherein upon adding a second switching network 12A to comprise the third integrated circuit die, the controller circuits 51 and 59A would further be electrically coupled to control switching of the plurality of third switches 52A and 52B and fourth switches 54A and 54B); and wherein at least one of the plurality of first switches and the plurality of second switches has a different current rating than at least one of the plurality of third switches and the plurality of fourth switches (52A, 52B, 54A and 54B, Fig. 115, paragraph [0380] describes wherein the stack switches 52A and 52B of the plurality of first switches and the third plurality of switches are manufactured to experience higher voltages or currents than the phase switches 54A and 54B of the plurality of second switches and the plurality of fourth switches resulting in at least one of the plurality of first switches having a different current rating than at least one of the plurality of fourth switches).
Therefore, given the teachings of Giuliano, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Li in view of Giuliano by employing the integrated circuit dies, switches and switched capacitor circuits.
Regarding claims 14-16 and 25, it is well-known in the art that surface-mount package (SMT) offers low-cost, automated assembly and easy inspection but may have larger size and higher parasitic inductance; flat no-lead (DFN) provides a compact footprint and good thermal/electrical performance, but has limited pin count and difficult inspection/rework; quad flat no-lead (QFN) delivers excellent thermal and electrical performance with high pin density, but requires hidden-joint inspection and more challenging rework; and flip-chip bonding provides the shortest electrical interconnections, excellent electrical and thermal performance, and high I/O density but requires precise alignment, underfill and has higher manufacturing complexity and cost.
Regarding claim 17, the combination of Li and Giuliano discloses the apparatus of claim 12, wherein the first integrated circuit die includes a first replica switch (Giuliano, 12A, Fig. 62, paragraph [0300] describes wherein the switching network 12A such as found in the first integrated circuit die may comprise a first set of first and second switches 1 and 2 on a left side of the switching network 12A and a second set of first and second switches 1 and 2 replicated on a right side of the switching network 12A), wherein at least two terminals of the first replica switch are electrically connected to at least two corresponding terminals of one switch of the plurality of first switches or the plurality of second switches (Giuliano, 12A, Fig. 62, paragraph [0300] describes wherein first switches 1 of both the first switches and first replica switches are in a complementary state and can be seen sharing a same input terminal Vin and output terminal to a second switching network 12D).
Regarding claim 19, the combination of Li and Giuliano discloses the apparatus of claim 17, wherein the first replica switch senses a current flowing through the one switch to which its terminals are electrically connected (Giuliano, 1 and 12A, Fig. 62).
Regarding claim 20, the combination of Li and Giuliano discloses the apparatus of claim 17, wherein the first replica switch detects a fault associated with the one switch to which its terminals are electrically connected (Giuliano, 1 and 12A, Fig. 62).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Giuliano, as applied above, and further in view of Bhagavat et al. (Pub. No. US 2020/0066677 A1, herein Bhagavat).
Regarding claim 13, the previous combination does not specifically state wherein the first switched capacitor circuit has a power rating of about 100 Watts to about 1,000 Watts.
However, in the same field of endeavor, Bhagavat teaches a similar apparatus, wherein the first switched capacitor circuit has a power rating of about 100 Watts to about 1,000 Watts (302 and 304, Fig. 3, paragraph [0025] describes integrated voltage regulator dies 302 and 304 which can sustain the introduction of 400 to 700 watts power to the integrated circuit package resulting in a first integrated circuit die comprising a first switched capacitor circuit such as described in paragraph [0031] having a power rating of about 100 Watts to about 1,000 Watts).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of previous combination with Bhagavat to further disclose wherein a first switched capacitor circuit has a power rating of about 100 Watts to about 1,000 Watts in order to provide the advantage of providing power semiconductor dies which can sustain requirements for substantially large currents preventing undesirable device characteristics when large power ratings are introduced into the apparatus (Bhagavat, paragraph [0025]).
Allowable Subject Matter
Claims 18, 21-24 and 28-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 18, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein the first replica switch is smaller in size than the one switch to which its terminals are electrically connected. Claims 21-24 are included likewise as they depend from claim 18.
Regarding claim 28, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein the first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source and drain terminals of the plurality of first switches or the plurality of second switches. Claim 29 is included likewise as it depends from claim 28.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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July 25, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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