DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, 9-10, and 18 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura).
Regarding claim 1, Ohmura discloses a manufacturing method for an epitaxial substrate, comprising:
patterning a substrate to form a trench (patterned layer-stack: insulating film 13 on semiconductor 11 {spaces between 13 exposing 11 constitute trenches}; Figs 1,2; Col 3, line 33 – Col 4, line 15);
manufacturing a transition layer (amorphous semiconductor film 14, for example, silicon; Fig 2; Col 4, lines 14-29) in the trench, and
performing crystal plane transformation processing on the transition layer based on a shape of the trench (annealing to form monocrystalline silicon based on the sidewall direction of the trench; Col 4 lines 30 – 60, Col 3, lines 3 line 57 – Col 4, line 8) , so as to transform the transition layer into a single crystal layer, wherein a surface, away from the substrate, of the single crystal layer is a (111) crystal plane (the disclosure is applicable to more than one crystal plane, as desired; a specific (111) crystal plane example is provided in EXAMPLE 1 { Col 5, lines 30 – 65}).
Regarding claim 2, Ohmura discloses the method according to claim 1, wherein the trench comprises a cross-section parallel to a plane where the substrate is located (as shown in Fig 1, the described parallel cross-section comprises parallel strips are stripes between each patterned 13), and the performing crystal plane transformation processing on the transition layer based on a shape of the trench, comprises:
performing the crystal plane transformation processing on the transition layer, based on a shape of the cross-section (the shape being the sidewall of the trench formed between strips of patterned 13 being aligned with the (110) crystal plane direction {EXAMPLE 1; Col 5, lines 35-40, 61-65}).
Regarding claim 3, Ohmura discloses the method according to claim 2, wherein the crystal plane transformation processing comprises at least high-temperature annealing processing (as applied to claim 1; Col 4, lines 30 – 53).
Regarding claim 7, Ohmura discloses the method according to claim 3, wherein the high-temperature annealing processing is laser annealing processing (Col 4, lines 59-60).
Regarding claim 9, Ohmura discloses the method according to claim 1, wherein the single crystal layer is made of a single crystal silicon (as applied to claim 1).
Regarding claim 10, Ohmura discloses the method according to claim 9, wherein the transition layer is made of an amorphous silicon or a polycrystalline silicon (as applied to claim 1).
Regarding claim 18, Ohmura discloses an epitaxial substrate, comprising:
a substrate (13,11; Figs 1-2; Col 3, line 33 – Col 4, line 15), wherein a trench (a space between 13 exposing 11 constitutes a trench) is disposed on a side of the substrate; and
a single crystal layer (the annealed semiconductor film 14, for example, silicon; Fig 2; Col 4 lines 30 – 60, Col 3, lines 3 line 57 – Col 4, line 8), wherein the single crystal layer is disposed in the trench, and a surface, away from the substrate, of the single crystal layer, is a (111) crystal plane (the disclosure is applicable to more than one crystal plane, as desired; a specific (111) crystal plane example is provided in EXAMPLE 1 { Col 5, lines 30 – 65}).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura) in view of Ohmi; Tadahiro et al. (US 5362672; hereinafter Ohmi).
Regarding claim 4, Ohmura discloses the method according to claim 3, wherein the transition layer is transformed into the single crystal layer by the high-temperature annealing processing (as applied to claim 1), but does not disclose wherein when the shape of the cross-section is a triangle or a hexagon.
In the same field of endeavor, Ohmi discloses a related method of forming an epitaxial substrate, wherein when the shape of a cross-section of a trench (the opening in pattern 601 exposing 602; Figs 6A,6B; analogous to 201,202 of Fig 2B, Col 4, lines 1-28) is a triangle or a hexagon (Figs 6A,6B; Col 4, lines 15-28, Col 7, lines 24-31), a single crystal layer of (111) orientation is formed.
Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the shape of a cross-section of a trench, being the basis for crystal plane orientation and being a triangle or a hexagon, as taught by Ohmi, with the method of claim 1 to arrive at claim 4. One would have been motivated to do this as an alternate pattern to produce a desired crystal plane orientation as compared to the strips or stripes disclosed by Ohmura. One would have had a reasonable expectation of success because the patterning methods are well-known in the art.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura) in view of ) in view of Ohmi; Tadahiro et al. (US 5362672; hereinafter Ohmi) and further in view of Gehrke, Thomas et al. (US 20020069816; hereinafter Gehrke).
Regarding claim 5, Ohmura in view of Ohmi discloses the method according to claim 3, wherein the transition layer is transformed into the single crystal layer by the high-temperature annealing processing (as applied to claim 1), but does not disclose wherein when the shape of the cross-section is a rectangle.
In the same field of endeavor, Ohmi discloses a related method of forming an epitaxial substrate, wherein when the shape of a cross-section of a trench (the opening in pattern 201 exposing 202; Figs 2A,2B; Col 4, lines 1-28) is a square (Figs 6A,6B; Col 4, lines 15-28, Col 7, lines 24-31), a single crystal layer of (100) orientation is formed.
Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the shape of a cross-section of a trench, being the basis for crystal plane orientation and being a square, as taught by Ohmi. One would have been motivated to do this as an alternate pattern to produce a desired crystal plane orientation as compared to the strips or stripes disclosed by Ohmura. One would have had a reasonable expectation of success because the patterning methods are well-known in the art.
Ohmura in view of Ohmi does not disclose the crystal plane transformation processing further comprises alkaline solution processing on an original single crystal layer formed by the high temperature annealing processing, and performing the alkaline solution processing on a surface, away from the substrate, of the original single crystal layer by using an alkaline solution, to obtain the single crystal layer.
In the same field of endeavor, Gehrke discloses alkaline solution processing (wet-etching in KOH; ¶ [0011]) a (100) single crystal layer to obtain a (111) single crystal layer (¶ [0011]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the alkaline solution processing taught by Gehrke with Ohmura in view of Ohmi to arrive at claim 5. One would have been motivated to do this as an alternate method of forming the (111) single crystal layer versus using different mask patterns in order to form (111) versus (100) oriented single crystal, and/or to provide manufacturing flexibility as to the manufacturing equipment used and/or for inventory control. In other words, for example, in the case where one has produced (100) oriented crystal using a rectangular mask (an original single crystal layer) or has only a rectangular mask available, one may transform the original (100) single crystal layer to (111) using the alkaline solution processing. One would have had a reasonable expectation of success because the alkaline processing method is well-known in the art (Gehrke; ¶ [0027]).
Regarding claim 6, Ohmura in view of Ohmi discloses the method according to claim 5, wherein the surface, away from the substrate, of the original single crystal layer, is a (100) crystal plane (as explained for claim 5).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura)
Regarding claim 8, Ohmura discloses the method according to claim 7, wherein a laser temperature range of the laser annealing processing is 500-1400℃ (Col 4, lines 30-53).
Ohmura does not disclose a laser energy density range of the laser annealing processing is 400-3000mJ/cm², but this would have been obvious to a person having ordinary skill in the art since this is a common energy density range for laser annealing well-known and commonly used in the art.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura) in view of Yoshida; Tomosuki et al. (EP-1638136-A1; hereinafter Yoshida).
Regarding claim 11, Ohmura discloses the method according to claim 1, comprising: manufacturing the transition layer (14; Fig 2) on a whole surface of the substrate (Col 4, lines 16-19), wherein the trench is filled with the transition layer (as shown in Fig 2, and as applied to claim 1); and performing the crystal plane transformation processing on the transition layer to transform the transition layer into the single crystal layer (as applied to claim 1).
Ohmura does not disclose polishing the transition layer until the substrate is exposed.
In the same field of endeavor, Yoshida discloses manufacturing method for an epitaxial substrate comprising: manufacturing an epitaxial layer (3; Fig 6; ¶ [0044]) on a whole surface of a substrate, wherein a trench (11; Figs 4-6; ¶ [0044]) is filled with the epitaxial layer; and, polishing the epitaxial layer until the substrate is exposed (Fig 6; ¶ [0044]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the polishing to expose the substrate of Yoshida with the method of claim 1 to result in an epitaxial layer in a trench but not on the upper substrate surface. One would have been motivated to do this, for example, as a means to achieve electrical isolation (the substrate between the epitaxial layer filled trenches) between trench regions and/or to form structures such as the vertical additional regions described by Yoshida (Figs 1-2; ¶ [0002-6]). One would have had a reasonable expectation of success because such polishing is well-known in the art for removing a surface layer after a trench fill process.
Regarding claim 12, Ohmura discloses the method according to claim 1, comprising: manufacturing the transition layer (14; Fig 2) on a whole surface of the substrate (Col 4, lines 16-19), wherein the trench is filled with the transition layer (as shown in Fig 2, and as applied to claim 1); and performing the crystal plane transformation processing on the transition layer to transform the transition layer into the single crystal layer (as applied to claim 1).
Ohmura does not disclose polishing the transition layer until the substrate is exposed.
In the same field of endeavor, Yoshida discloses manufacturing method for an epitaxial substrate comprising: manufacturing an epitaxial layer (3; Fig 6; ¶ [0044]) on a whole surface of a substrate, wherein a trench (11; Figs 4-6; ¶ [0044]) is filled with the epitaxial layer; and, polishing the epitaxial layer until the substrate is exposed (Fig 6; ¶ [0044]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the polishing to expose the substrate of Yoshida with the method of claim 1 to result in an epitaxial layer in a trench but not on the upper substrate surface. One would have been motivated to do this, for example, as a means to achieve electrical isolation (the substrate between the epitaxial layer filled trenches) between trench regions and/or to form structures such as the vertical additional regions described by Yoshida (Figs 1-2; ¶ [0002-6]). One would have had a reasonable expectation of success because such polishing is well-known in the art for removing a surface layer after a trench fill process.
Claims 13-14, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura) in view of Kreiner; Laura et al. (US 2025/0007246; hereinafter Kreiner).
Regarding claim 13, Ohmura discloses the method according to claim 1, but does not disclose further comprising: growing an epitaxial structure layer on a side, away from the substrate, of the single crystal layer.
In the same field of endeavor, Kreiner discloses a related method for forming semiconductor laser diodes comprising growing an epitaxial structure layer (4/42; Fig 4; ¶ [0062]) on a side, away from a substrate (1; Fig 4; ¶ [0062]), of a crystalline layer (3; Fig 4; ¶ [0062,0011-13]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to grow an epitaxial structure layer according to claim 13. One would have been motivated to do this in order to form a semiconductor device, such as the laser diode disclosed by Kreiner, and would have had a reasonable expectation of success because it is well-known in the art to form a structure layer for a device on an epitaxial substrate (sometimes known in the art as a growth substrate).
Regarding claim 14, Ohmura in view of Kreiner discloses the method according to claim 13, wherein an orthographic projection area, on a plane where the substrate is located, of the epitaxial structure layer (Kreiner; 4/42; Fig 4), is consistent with an orthographic projection area, on the plane where the substrate is located, of the single crystal layer, or an orthographic projection width, on the plane where the substrate is located, of the epitaxial structure layer, is consistent with an orthographic projection width, on the plane where the substrate is located, of the single crystal layer (Kreiner; as shown in Figs 3-4, layer 4 is formed only on layer 3, both being confined to the region between opening 21 in layer 2 {thereby having a consistent width}; ¶ [0062]).
Regarding claim 16, Ohmura in view of Kreiner discloses the method according to claim 13, wherein the epitaxial structure layer (Kreiner; 4/42; Fig 4) comprises a first semiconductor layer and a second semiconductor layer that have opposite conductivity types, and an active region disposed between the first semiconductor layer and the second semiconductor layer (¶ [0014, 0062]).
Regarding claim 19, Ohmura discloses a semiconductor structure, comprising a substrate, comprising:
a substrate (13,11; Figs 1-2; Col 3, line 33 – Col 4, line 15), wherein a trench (a space between 13 exposing 11 constitutes a trench) is disposed on a side of the substrate; and
a single crystal layer (the annealed semiconductor film 14, for example, silicon; Fig 2; Col 4 lines 30 – 60, Col 3, lines 3 line 57 – Col 4, line 8), wherein the single crystal layer is disposed in the trench, and a surface, away from the substrate, of the single crystal layer, is a (111) crystal plane (the disclosure is applicable to more than one crystal plane, as desired; a specific (111) crystal plane example is provided in EXAMPLE 1 { Col 5, lines 30 – 65}).
Ohmura does not disclose an epitaxial structure layer, wherein the epitaxial substrate layer is disposed on a side, away from the substrate, of the single crystal layer.
In the same field of endeavor, Kreiner discloses a laser diode comprising an epitaxial structure layer (4/42; Fig 4; ¶ [0062]) on a side, away from a substrate (1; Fig 4; ¶ [0062]), of a crystalline layer (3; Fig 4; ¶ [0062,0011-13]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the epitaxial structure layer of Kreiner with that of Ohmura to arrive at the semiconductor structure of claim 13. One would have been motivated to do this in order to take advantage of Ohmura’s method of forming the (111) single crystal layer to form a semiconductor device, such as the laser diode disclosed by Kreiner, and would have had a reasonable expectation of success because it is well-known in the art to form a structure layer for a device on an epitaxial substrate (sometimes known in the art as a growth substrate).
Regarding claim 20, Ohmura in view of Kreiner discloses the semiconductor structure according to claim 19, wherein the epitaxial structure layer (Kreiner; 4/42; Fig 4) comprises a first semiconductor layer and a second semiconductor layer that have opposite conductivity types, and an active region disposed between the first semiconductor layer and the second semiconductor layer (¶ [0014, 0062]).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura) in view of Kreiner; Laura et al. (US 2025/0007246; hereinafter Kreiner) and further in view of Brueck; Steven R. J. et al. (US 2020/0212198; hereinafter Brueck).
Regarding claim 15, Ohmura in view of Kreiner discloses the semiconductor structure according to claim 13, but does not disclose wherein an orthographic projection area, on a plane where the substrate is located, of the epitaxial structure layer (Kreiner; 4/42; Fig 4), is greater than an orthographic projection area, on the plane where the substrate is located, of the single crystal layer, or an orthographic projection width, on the plane where the substrate is located, of the epitaxial structure layer, is greater than an orthographic projection width, on the plane where the substrate is located, of the single crystal layer.
In the same field of endeavor, Brueck discloses a method comprising forming an epitaxial layer (20; Fig 1E; ¶ [0042]) on a seed area (12 {26}, comprising a single crystal layer, such as silicon; Figs 1E, {2E}, 4; ¶ [0034]), wherein a width of the epitaxial layer is greater than a width of the seed area (as show in Figs 1E, 4). Accordingly, it would have been obvious to a person having ordinary skill in the art that an epitaxial structure layer such as that of claim 13 may be formed to satisfy claim 20. One may have been motivated to do this for a number of structural or manufacturing reasons, and would have had a reasonable expectation of success because of the similar epitaxial processes.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ohmura; Yamichi et al. (US 4500388; hereinafter Ohmura) in view of Soussan; Philippe et al. (US 2021/0111021; hereinafter Sousson).
Regarding claim 17, Ohmura discloses the method according to claim 2, but does not disclose wherein a lower surface of the single crystal layer is not parallel to the plane where the substrate is located, and the single crystal layer is a pyramid or a combination of a pyramid and a prism.
In the same field of endeavor, Soussan discloses a method of epitaxial growth a lower surface of the epitaxial layer is not parallel to the plane where the substrate is located, and the epitaxial layer is a pyramid (17; Fig 6B; ¶ [0075-76]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the teaching of Soussan with the method of claim 2. One would have been motivated to do this for an application such as one where a photodiode will be formed above the lower surface and the pyramid shape may increase the amount of internal reflection and therefore also increase the quantum efficiency of the photodiode, as taught by Soussan (¶ [0034]). One would have had a reasonable expectation of success due to the similar method of forming an epitaxial layer in a trench of both Soussan and Ohmura.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nishimura; Takehiro et al. (US 2019/0237323);
Gunji; Isao et al. (US 2015/0001588).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817