Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant elected Group II, claims 12-20, without traverse and first device species directed to Fig. 17 with traverse. Claims 1-11 have been canceled and new claims 21-31 have been added. Currently, claims 12-31 are pending.
Because applicant did not distinctly and specifically point out the supposed errors in the species restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Allegato et al. (Pub. No. US 2015/0115378 A1, herein Allegato).
Regarding claim 12, Allegato discloses a device, comprising: a first die 34 of semiconductor integrating electronic components (Allegato: Fig. 2 and paragraph [0018]); a second die 36/38 of semiconductor bonded to the first die and forming patterned structures (Allegato: Fig. 2 and paragraph [0023]), the first die having a main surface; internal electrical coupling structures 44/50 electrically coupling the main surface of the first die to the second die (Allegato: Fig. 2 and paragraphs [0020]-[0023]); and external connection regions 46/46 on the main surface of the first die; and a package 94/96 packaging on the main surface of the first die (Allegato: Fig. 2 and paragraphs [0021], [0035]).
Regarding claim 13, Allegato discloses the device according to claim 12, wherein the package entirely covers the main surface of the first die (Allegato: Fig. 2 and paragraphs [0009], [0035]).
Regarding claim 14, Allegato discloses the device according to claim 12, further comprising a bonding layer 54 superimposed on the main surface of the first die (Allegato: Fig. 2 and paragraph [0023]).
Regarding claim 15, Allegato inherently discloses the device according to claim 14, wherein the bonding layer has through openings and the external connection regions traverse the through openings (Allegato: Fig. 2 and paragraphs [0021], [0069]; “It is possible to apply the present manufacturing method also to packages of a different type, such as for example packages of a ball grid array (BGA), quad-flat no-leads (QFN), or chip-scale (CSP) type.” A BGA with this structure uses a bonding layer that has vertical openings or vias, while conductive external connection regions are routed laterally across that layer, sometimes intersecting or connecting through those openings to efficiently link the chip to the solder ball array.).
Regarding claim 16, Allegato discloses a MEMS device, comprising: a first die 34 that includes: a main surface; a body 40 and a passivation layer 42 on the body (Allegato: Fig. 2 and paragraphs [0018]-[0020]); a second die 38 having a first semiconductor layer 62 and an anchoring region 70 on the first semiconductor layer, the second die bonded to the first die by a bonding region and forming patterned structures (Allegato: Fig. 2 and paragraphs [0018]-[0019], [0026]-[0029]); a first contact pad 46 and a second contact pad 48 on the passivation layer (Allegato: Fig. 2 and paragraphs [0021]-[0022]); a fixed portion on the first semiconductor layer opposite to the anchoring region (the layer underneath pad 76); and a third contact pad 76 on the fixed portion (Allegato: Fig. 2 and paragraph [0031]).
Regarding claims 17-18, Allegato discloses the MEMS device of claim 16, further comprising a first recess 72, a second recess, and a third recess, further comprising a through opening that incorporates a part of the third recess (Allegato: Fig. 2 and paragraphs [0030], [0045]). This limitation appears to be a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is taught by the reference even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 19, Allegato discloses the device according to claim 16, wherein the passivation layer includes embedded metallizations 44 (Allegato: Fig. 2 and paragraphs [0010], [0020], [0022]).
Regarding claim 20, Allegato discloses the device according to claim 16 further comprising external connection regions 80 on the first contact pads, the external connection regions protruding partially from the device (Allegato: Fig. 2 and paragraph [0031]).
Regarding claim 21, Allegato discloses a device, comprising: a first die 34 including: a semiconductor body 40; and a passivation layer 42 on the body (Allegato: Fig. 2 and paragraphs [0018]-[0020]); a second die 38 including: a first semiconductor layer 62; and a first anchoring region 70 on the first semiconductor layer; a first bonding region coupled between the semiconductor body and the first anchoring region (Allegato: Fig. 2 and paragraphs [0018]-[0019], [0026]-[0029]); a first contact pad 46 on the passivation layer; a fixed portion on the first semiconductor layer; and a second contact pad 76 on the fixed portion (Allegato: Fig. 2 and paragraphs [0021]-[0022], [0031]; The layer underneath pad 76 is the fixed portion.).
Regarding claim 22, Allegato discloses the device according to claim 21, wherein the semiconductor body includes a plurality of electronic components (Allegato: Fig. 2 and paragraphs [0022], [0031]).
Regarding claim 23, Allegato discloses the device according to claim 21, wherein the passivation layer includes a plurality of metallizations 44 forming a redistribution layer (Allegato: Fig. 2 and paragraphs [0020], [0022]).
Regarding claim 24, Allegato discloses the device according to claim 21, wherein the second die further includes: a second anchoring region on the first semiconductor layer; and a plurality of suspended structures between the first and second anchoring region (Allegato: Fig. 2 and paragraphs [0026]-[0029]).
Regarding claim 25, Allegato discloses the device according to claim 21, wherein the first and second contact pads are coupled together with a bonding wire (Allegato: Fig. 2 and paragraphs [0021]-[0022]).
Regarding claim 26, Allegato discloses the device according to claim 21, further comprising a third contact pad 48 on the passivation layer (Allegato: Fig. 2 and paragraphs [0021]-[0022]).
Regarding claim 27, Allegato discloses the device according to claim 26, further comprising a metal bump on the third contact pad (Allegato: Fig. 2 and paragraph [0069]).
Regarding claim 28, Allegato discloses the device according to claim 21, wherein the first anchoring region includes: a dielectric region on the first semiconductor layer; a second semiconductor layer on the dielectric region; and a second bonding region on the second semiconductor layer (Allegato: Fig. 2 and paragraphs [0027]-[0029]).
Regarding claim 29, Allegato discloses the device according to claim 21, wherein the fixed portion includes: a dielectric region on the first semiconductor layer; a second semiconductor layer on the dielectric region; and the second contact pad 76 on the second semiconductor layer (Allegato: Fig. 2 and paragraphs [0027]-[0029], [0031]).
Regarding claim 30, Allegato discloses the device according to claim 24, wherein the first die includes a first cavity 72 in a face of the semiconductor body opposite the passivation layer (Allegato: Fig. 2 and paragraphs [0019]-[0020]).
Regarding claim 31, Allegato discloses the device according to claim 30, wherein the plurality of suspended structures of the second die is aligned with the first cavity in the first die (Allegato: Fig. 2 and paragraphs [0019]-[0020], [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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April 2, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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