Prosecution Insights
Last updated: August 17, 2026
Application No. 18/489,746

PANEL LEVEL SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §103
Filed
Oct 18, 2023
Priority
Oct 27, 2022 — provisional 63/419,799
Examiner
NGUYEN, SOPHIA T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
2 (Final)
45%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
59%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
234 granted / 520 resolved
-23.0% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
73 currently pending
Career history
614
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
14.8%
-25.2% vs TC avg
§112
26.5%
-13.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 520 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendment dated 05/27/2026, in which claims 1-6 were cancelled, claims 7, 12, 14-15, 21 were amended, has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7-15, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20190139925) in view of Tuominen (US Pub. 20160174387) and Arthur et al. (US Pub. 20080190748). Regarding claim 7, Yu et al. discloses in Fig. 2A-Fig. 2G a method, comprising: forming a dielectric adhesive layer [116] on a temporary adhesion layer [114] on a carrier [112][Fig. 2A, paragraph [0017]]; forming an opening [116a] extending through the dielectric adhesive layer [116][Fig. 2B]; coupling a semiconductor die [120] to the dielectric adhesive layer [116] including overlapping and aligning a contact pad [121] of the semiconductor die [120] with the opening [116a][Fig. 2C]; forming an encapsulant [150] on the dielectric adhesive layer [116], on a surface of the semiconductor die [120], and on a first sidewall of the semiconductor die [120] transverse to the surface of the semiconductor die [120][Fig. 2D]; removing the dielectric adhesive layer [116], the semiconductor die [120], and the encapsulant [150] from the temporary adhesion layer [114] on the carrier [112] and from the carrier [112] exposing the opening [116a][Fig. 2F]; and forming a conductive structure [M0] in the opening [116a] and on a surface of the contact pad [121][Fig. 2G]. Yu et al. fails to disclose forming the dielectric adhesive layer on the temporary adhesion layer comprising: forming an insulating layer on the temporary adhesion layer on the carrier; forming an adhesive layer on the insulating layer. However, Yu et al. discloses in paragraph [0017] that “the bonding layer 116 may be a photosensitive adhesive layer made of a photosensitive adhesive material, such as polyimide, benzocyclobutene (BCB), SINR, or combinations thereof.” Tuominen discloses in Fig. 14, Fig. 15 forming the dielectric adhesive layer [4, 6,17 and 7] on the temporary adhesion layer [3] comprising: forming an insulating layer [4 and 6] on the temporary adhesion layer [3] on the carrier [2]; forming an adhesive layer [17 and 7] on the insulating layer [4]. Tuominen further discloses in Fig. 17 coupling the semiconductor die [8] to the adhesive layer [7 and 17]; forming the encapsulant [11] on the adhesive layer [7 and 17]; removing the insulating layer [4 and 6], the adhesive layer [7 and 17], the semiconductor die [8], and the encapsulant [11] from the temporary adhesion layer [3] on the carrier [2] and from the carrier [2]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tuominen into the method of Yu et al. to include forming the dielectric adhesive layer on the temporary adhesion layer comprising: forming an insulating layer on the temporary adhesion layer on the carrier; forming an adhesive layer on the insulating layer. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing suitable configuration of the dielectric adhesive layer to avoid any voids in the insulation between conductive structures and the semiconductor die, to adjust or set the dielectric properties of the insulating layer between the semiconductor die and the conductive structures and/or to adjust or set the distance between the semiconductor die and the conductive structures [paragraph [0076] of Tuominen]. Incorporating the dielectric adhesive layer disclosed by Tuominen into the method of Yu et al. would result to the limitations “forming the opening through the insulating layer and the adhesive layer; coupling the semiconductor die to the adhesive layer; forming the encapsulant on the adhesive layer; removing the insulating layer, the adhesive layer, the semiconductor die, and the encapsulant from the temporary adhesion layer on the carrier and from the carrier exposing the opening.” Yu et al. and Tuominen fails to disclose after forming the opening, coupling the semiconductor die to the adhesive layer; wherein the opening is empty when coupling the semiconductor die to the adhesive layer. Arthur et al. discloses in Fig. 5-Fig. 6 after forming the opening [118], coupling the semiconductor die [120] to the adhesive layer [110]; wherein the opening [118] is empty when coupling the semiconductor die [120] to the adhesive layer [110]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Arthur et al. into the method of Yu et al. and Tuominen to include after forming the opening, coupling the semiconductor die to the adhesive layer; wherein the opening is empty when coupling the semiconductor die to the adhesive layer. The ordinary artisan would have been motivated to modify Yu et al. and Tuominen in the above manner for the purpose of providing suitable order for performing the step of coupling the semiconductor die to the adhesive layer. Further, “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results” In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Regarding claim 8, Yu et al. fails to disclose wherein forming the opening through the insulating layer and the adhesive layer to the temporary adhesion layer by exposing the insulating layer and the adhesive layer to a laser. However, Yu et al. discloses in Fig. 2B forming the opening through the dielectric adhesive layer [116] to the temporary adhesion layer [114]. Tuominen and Arthur disclose the dielectric adhesive layer comprising the insulating layer and the adhesive layer. Tuominen further discloses in paragraph [0068], [0081] an opening [5/13] is formed by exposing the insulating layer [4 and 6] and the adhesive layer [7 and 17] to a laser. Arthur et al. discloses in Fig. 5, paragraph [0031] forming the opening [118] through the insulating layer [100] and the adhesive layer [110] by exposing the insulating layer [100] and the adhesive layer [110] to a laser. Thus, the combination of Yu et al., Arthur et al. and Tuominen discloses “forming the opening through the insulating layer and the adhesive layer to the temporary adhesion layer by exposing the insulating layer and the adhesive layer to a laser.” It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Arthur et al. and Tuominen into the method of Yu et al. to include forming the opening through the insulating layer and the adhesive layer to the temporary adhesion layer by exposing the insulating layer and the adhesive layer to a laser. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing suitable method for forming the opening through the dielectric adhesive layer. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 9, Yu et al. discloses exposing the dielectric adhesive layer [116] to an etching includes stopping the etching once the etching reaches the temporary adhesion layer [114]. Tuominen and Arthur disclose the dielectric adhesive layer comprising the insulating layer and the adhesive layer. Arthur et al. discloses in Fig. 5, paragraph [0031] etching the insulating layer [100] and the adhesive layer [110] by exposing the insulating layer [100] and the adhesive layer [110] to a laser. Tuominen further discloses in paragraph [0068], [0081] etching the insulating layer [4 and 6] and the adhesive layer [7 and 17] by exposing the insulating layer [4 and 6] and the adhesive layer [7 and 17] to the laser. Thus, the combination of Yu et al., Arthur et al. and Tuominen would result to “wherein exposing the insulating layer and the adhesive layer to the laser includes stopping the laser once the laser reaches the temporary adhesion layer.” Regarding claim 10, Yu et al. discloses in Fig. 2E removing a portion of the encapsulant [150] to expose the surface of the semiconductor die [120A]. Regarding claim 11, Yu et al. discloses in Fig. 2C wherein forming the opening [116a] includes forming the opening [116a] extending to the temporary adhesion layer [114]. Regarding claim 12, Yu et al. discloses in Fig. 2A-Fig. 2G a method, comprising: forming a panel wafer including: forming a dielectric adhesive layer [116] on a temporary adhesion layer [114] on a carrier [112][Fig. 2A, paragraph [0017]]; forming a plurality of openings [116a] extending through the dielectric adhesive layer [116][Fig. 2B]; coupling a plurality of dies [120] to the dielectric adhesive layer [116], each die of the plurality of dies overlapping at least one opening of the plurality of openings [116a][Fig. 2C]; and forming an encapsulant [150] on the dielectric adhesive layer [116], on a surface of the semiconductor die [120], and on a first sidewall of the semiconductor die [120] transverse to the surface of the semiconductor d the plurality of dies [120][Fig. 2D]; Yu et al. fails to disclose forming the dielectric adhesive layer on the temporary adhesion layer comprising: forming an insulating layer on the temporary adhesion layer on the carrier; forming an adhesive layer on the insulating layer. However, Yu et al. discloses in paragraph [0017] that “the bonding layer 116 may be a photosensitive adhesive layer made of a photosensitive adhesive material, such as polyimide, benzocyclobutene (BCB), SINR, or combinations thereof.” Tuominen discloses in Fig. 14, Fig. 15 forming the dielectric adhesive layer [4, 6,17 and 7] on the temporary adhesion layer [3] comprising: forming an insulating layer [4 and 6] on the temporary adhesion layer [3] on the carrier [2]; forming an adhesive layer [17 and 7] on the insulating layer [4]. Tuominen further discloses in Fig. 17 coupling the plurality of dies [8] to the adhesive layer [7 and 17]; forming the encapsulant [11] on the adhesive layer [7 and 17]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tuominen into the method of Yu et al. to include forming the dielectric adhesive layer on the temporary adhesion layer comprising: forming an insulating layer on the temporary adhesion layer on the carrier; forming an adhesive layer on the insulating layer. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing suitable configuration of the dielectric adhesive layer to avoid any voids in the insulation between conductive structures and the semiconductor die, to adjust or set the dielectric properties of the insulating layer between the semiconductor die and the conductive structures and/or to adjust or set the distance between the semiconductor die and the conductive structures [paragraph [0076] of Tuominen]. Incorporating the dielectric adhesive layer disclosed by Tuominen into the method of Yu et al. would result to the limitations “forming the plurality of openings through the insulating layer and the adhesive layer; coupling the plurality of dies to the adhesive layer; forming the encapsulant on the adhesive layer”. Yu et al. and Tuominen fails to disclose after forming the plurality of openings, coupling the plurality of dies to the adhesive layer; wherein the plurality of openings are empty when coupling the plurality of openings to the adhesive layer. Arthur et al. discloses in Fig. 5-Fig. 6 after forming the plurality of openings [118], coupling the plurality of dies [120] to the adhesive layer [110]; wherein the plurality of openings [118] are empty when coupling the plurality of dies [120] to the adhesive layer [110]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Arthur et al. into the method of Yu et al. and Tuominen to include after forming the plurality of openings, coupling the plurality of dies to the adhesive layer; wherein the plurality of openings are empty when coupling the plurality of openings to the adhesive layer. The ordinary artisan would have been motivated to modify Yu et al. and Tuominen in the above manner for the purpose of providing suitable order for performing the step of coupling the semiconductor die to the adhesive layer. Further, “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results” In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Regarding claim 13, Yu et al. fails to disclose wherein forming the plurality of openings including exposing the adhesive layer and the insulating layer to a laser. Arthur et al. discloses in Fig. 5, paragraph [0031] forming the plurality of openings [118] including exposing the insulating layer [100] and the adhesive layer [110] to a laser. Tuominen further discloses in paragraph [0068], [0081] forming the plurality of openings opening [13] including exposing the insulating layer [4 and 6] and the adhesive layer [7 and 17] to a laser. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tuominen into the method of Yu et al. to include wherein forming the plurality of openings including exposing the adhesive layer and the insulating layer to a laser. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing suitable method for forming the opening through the dielectric adhesive layer. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 14, Yu et al. discloses in Fig. 2C wherein coupling the plurality of die [120A] to the dielectric adhesive layer [116] includes aligning a contact pad [121] of each die of the plurality of die [120] with at least one opening [116a] of the plurality of openings [116a]. Tuominen discloses in Fig. 17 the dielectric adhesive layer [4, 6,17 and 7] comprising the insulating layer [4 and 6] and the adhesive layer [7 and 17]; and coupling the plurality of dies [8] to the adhesive layer [7 and 17]. Arthur et al. discloses in Fig. 6, paragraph [0033] wherein coupling the plurality of dies [120, 121] to the adhesive layer [110] includes aligning a contact pad [122] of each die of the plurality of die dies [120 and 121] with at least one opening of the plurality of openings [118]. Thus, the combination of Yu et al., Arthur et al. and Tuominen would result “wherein coupling the plurality of die to the adhesive layer includes aligning a contact pad of each die of the plurality of die with at least one opening of the plurality of openings.” Regarding claim 15, Yu et al. discloses in Fig. 2E removing a portion of the encapsulant [150] exposing respective surfaces of the plurality of die [120] facing away from the dielectric adhesive layer [116]. Tuominen discloses in Fig. 17 the dielectric adhesive layer [4, 6,17 and 7] comprising the insulating layer [4 and 6] and the adhesive layer [7 and 17]. Thus, the combination of Yu et al. and Tuominen would result to “removing a portion of the encapsulant exposing respective surfaces of the plurality of die facing away from the adhesive layer and the insulating layer.” Regarding claim 17, Yu et al. discloses Fig. 2G forming a plurality of conductive structures [M0] in the plurality of openings [116a]. Regarding claim 18, Yu et al. discloses in Fig. 2F removing the panel wafer from the temporary adhesion layer [114] of the carrier [112]. Regarding claim 19, Yu et al. discloses in Fig. 2G after removing the panel wafer from the temporary adhesion layer [114], forming a plurality of conductive structures [M0] in the plurality of openings [116a], each conductive structure of the plurality of conductive structures [M0] being in a corresponding opening of the plurality of openings [116a]. Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20190139925) in view of Tuominen (US Pub. 20160174387) and Arthur et al. (US Pub. 20080190748) as applied to claim 15 and claim 19 above and further in view of Chew (US Pub. 20200203188). Regarding claim 16, Yu et al., Arthur et al. and Tuominen fails to disclose singulating the panel wafer along a plurality of singulation lines, and wherein removing the portion of the encapsulant occurs before singulating the panel wafer along the plurality of singulation lines. Chew discloses in Fig. 9a-9b, Fig. 14, Fig. 15b, paragraph [0134], singulating the panel wafer along a plurality of singulation lines [cutting line], and wherein removing the portion of the encapsulant [123] occurs before singulating the panel wafer along the plurality of singulation lines [cutting line]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chew into the method of Yu et al., Arthur et al. and Tuominen to include singulating the panel wafer along a plurality of singulation lines, and wherein removing the portion of the encapsulant occurs before singulating the panel wafer along the plurality of singulation lines. The ordinary artisan would have been motivated to modify Yu et al., Arthur et al. and Tuominen in the above manner for the purpose of providing packaged chip. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 20, Yu et al., Arthur et al. and Tuominen fails to disclose after forming the plurality of conductive structures, singulating the panel wafer along a plurality of singulation lines, each singulation line of the plurality of singulation lines being between at least a pair of adjacent die of the plurality of die. Chew discloses in Fig. 14, paragraph [0134], after forming the plurality of conductive structures [111], singulating the panel wafer along a plurality of singulation lines [cutting line], each singulation line of the plurality of singulation lines being between at least a pair of adjacent die [106] of the plurality of dies [106]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chew into the method of Yu et al., Arthur et al. and Tuominen to include after forming the plurality of conductive structures, singulating the panel wafer along a plurality of singulation lines, each singulation line of the plurality of singulation lines being between at least a pair of adjacent die of the plurality of die. The ordinary artisan would have been motivated to modify Yu et al., Arthur et al. and Tuominen in the above manner for the purpose of providing packaged chip. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claims 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US Pub. 20090160071) in view of Yu et al. (US Pub. 20190139925) and Tuominen (US Pub. 20160174387). Regarding claim 21, Shen et al. discloses in Fig. 3-Fig. 8 a method, comprising: forming a bonding layer [30] on a carrier [20]; after forming the bonding layer [30], forming an opening [32] extending through the bonding layer [30]; after forming the opening [32] through the bonding layer [30], coupling a semiconductor die [410] to the bonding layer [30], coupling the semiconductor die [410] to the bonding layer [30] includes aligning a contact pad [412] of the semiconductor die [410] with the opening [32] to overlap the opening [32] with the contact pad [412], wherein the opening [32] is empty when coupling the semiconductor die [410] to the bonding layer [30]; forming an encapsulant [70] on the bonding layer [30] and on the semiconductor die [410] to enclose the semiconductor die [410] between the bonding layer [30] and the encapsulant [70]; removing the bonding layer [30], the semiconductor die [410], and the encapsulant [70] from the carrier [20] exposing the opening [32]; and forming a conductive structure [90] in the opening [32] and on a surface of the contact pad [412]. Shen et al. fails to disclose the bonding layer comprises a insulating layer and an adhesive layer; forming the bonding layer on the carrier comprising: forming an insulating layer on a temporary adhesion layer on a carrier; after forming the insulating layer on the temporary adhesive layer, forming an adhesive layer on the insulating layer; the opening extending through the insulating layer and the adhesive layer to the temporary adhesion layer; coupling the semiconductor die to the bonding layer comprising coupling the semiconductor die to the adhesive layer; the opening extends from the contact pad to the temporary adhesion layer; wherein the opening is empty when coupling the semiconductor die to the adhesive layer, and wherein coupling the semiconductor die to the adhesive layer includes contacting a respective surface of the contact pad with the adhesive layer; forming the encapsulant on the bonding layer to enclose the semiconductor die between the bonding layer and the encapsulant comprising forming the encapsulant on the adhesive layer to enclose the semiconductor die between the adhesive layer and the encapsulant; removing the bonding layer, the semiconductor die, and the encapsulant from the carrier comprising removing the insulating layer, the adhesive layer, the semiconductor die, and the encapsulant from the temporary adhesion layer on the carrier. Tuominen discloses in Fig. 14-Fig. 17 the bonding layer [4, 6, 7 and 17] comprises a insulating layer [4 and 6] and an adhesive layer [7 and 17]; forming the bonding layer on the carrier comprising: forming an insulating layer [4 and 6] on a temporary adhesion layer [3] on a carrier [2]; after forming the insulating layer [4 and 6] on the temporary adhesive layer [3], forming an adhesive layer [7 and 17] on the insulating layer [4 and 6]; coupling the semiconductor die [8] to the bonding layer [4, 6, 7 and 17] comprising coupling the semiconductor die to the adhesive layer [7 and 17]; forming the encapsulant [11] on the bonding layer [4, 6, 7 and 17] to enclose the semiconductor die [8] between the bonding layer [4, 6, 7 and 17] and the encapsulant [11] comprising forming the encapsulant [11] on the adhesive layer [7 and 17] to enclose the semiconductor die [8] between the adhesive layer [7 and 17] and the encapsulant [11]; removing the bonding layer [4, 6, 7 and 17], the semiconductor die [8], and the encapsulant [11] from the carrier comprising removing the insulating layer [4 and 6], the adhesive layer [7 and 17], the semiconductor die [8], and the encapsulant [11] from the temporary adhesion layer [3] on the carrier [2]. Yu et al. discloses in Fig. 2C the bonding layer [116 and 123] comprises a insulating layer [116] and an adhesive layer [123]; the opening [116a and 125a] extending through the insulating layer [116] and the adhesive layer [123] to the temporary adhesion layer [114]; coupling the semiconductor die [120] to the bonding layer [116 and 123] comprising coupling the semiconductor die [120] to the adhesive layer [123]; the opening [116a and 125a] extends from the contact pad [121] to the temporary adhesion layer [114]; wherein coupling the semiconductor die [120] to the adhesive layer [123] includes contacting a respective surface of the contact pad [121] with the adhesive layer [123]; removing the bonding layer, the semiconductor die, and the encapsulant from the carrier comprising removing the insulating layer [116], the adhesive layer [123], the semiconductor die [120], and the encapsulant [150] from the temporary adhesion layer [114] on the carrier. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tuominen and Yu et al. into the method of Shen et al. to include the bonding layer comprises a insulating layer and an adhesive layer; forming the bonding layer on the carrier comprising: forming an insulating layer on a temporary adhesion layer on a carrier; after forming the insulating layer on the temporary adhesive layer, forming an adhesive layer on the insulating layer; the opening extending through the insulating layer and the adhesive layer to the temporary adhesion layer; coupling the semiconductor die to the bonding layer comprising coupling the semiconductor die to the adhesive layer; the opening extends from the contact pad to the temporary adhesion layer; wherein the opening is empty when coupling the semiconductor die to the adhesive layer, and wherein coupling the semiconductor die to the adhesive layer includes contacting a respective surface of the contact pad with the adhesive layer; forming the encapsulant on the bonding layer to enclose the semiconductor die between the bonding layer and the encapsulant comprising forming the encapsulant on the adhesive layer to enclose the semiconductor die between the adhesive layer and the encapsulant; removing the bonding layer, the semiconductor die, and the encapsulant from the carrier comprising removing the insulating layer, the adhesive layer, the semiconductor die, and the encapsulant from the temporary adhesion layer on the carrier. The ordinary artisan would have been motivated to modify Shen et al. in the above manner for the purpose of providing suitable configuration of the bonding layer to ensure a good adhesion between the die and the bonding layer, to avoid any voids in the insulation between conductive structures and the semiconductor die, to adjust or set the dielectric properties of the insulating layer between the semiconductor die and the conductive structures and/or to adjust or set the distance between the semiconductor die and the conductive structures [paragraph [0022] of Yu et al., paragraph [0076] of Tuominen]; and providing carrier including a debond layer for bonding and debonding the carrier from the above layer(s) [paragraph [0016] of Yu et al., paragraph [0066] of Tuominen]. Shen et al. discloses after forming the bonding layer, forming the opening and after forming the opening, coupling the semiconductor die to the bonding layer. Incorporating the bonding layer comprising the insulating layer and the adhesive layer and an opening extends to the temporary adhesion layer as disclosed by Tuominen and Yu et al. into the method of Shen et al. would result to the limitations “after forming the adhesive layer on insulating layer, forming the opening through the insulating layer and the adhesive layer to the temporary adhesion layer and after forming the opening through the insulating layer and the adhesive layer to the temporary adhesion layer, coupling a semiconductor die to the adhesive layer.” Shen et al. discloses the opening [32] is empty when coupling the semiconductor die [410] to the bonding layer [30]. Tuominen and Yu et al. suggest coupling the semiconductor die to the bonding layer comprises coupling the semiconductor die to the adhesive layer of the bonding layer. Therefore, the combination of Shen et al., Tuominen and Yu et al. would result to “the opening is empty when coupling the semiconductor die to the adhesive layer.” Consequently, the combination of Shen et al., Tuominen and Yu et al. suggests every limitation of claim 21. Regarding claims 22-23, Shen et al. discloses in Figs. 5-7 wherein forming the conductive structure [90] in the opening [32] and on the surface of the contact pad [412] includes: forming a first portion of the conductive structure [90] in the opening [32]. forming a second portion of the conductive structure along a surface of the bonding layer [30], and the surface of the bonding layer [30] facing away from the semiconductor die [410]; forming a solder ball [420] on the second portion of the conductive structure [90]. Yu et al. and Tuominen discloses the surface of the bonding layer facing away from the semiconductor die is a surface of the insulating layer. Consequently, the combination of Shen et al., Yu et al. and Tuominen would result to “forming a second portion of the conductive structure along a surface of the insulating layer, and the surface of the insulating layer facing away from the semiconductor die.” Regarding claim 24, Shen et al. discloses in Fig. 4, Fig. 15 wherein forming encapsulant [70 or 700] on the semiconductor die [410] further includes forming the encapsulant [70 or 700] to cover a plurality of sidewalls of the semiconductor die [410] and cover a surface of the semiconductor die [410] facing away from the bonding layer [30]. Yu et al. and Tuominen suggests the bonding layer comprising the insulating layer and the adhesive layer. Thus, the combination of Shen et al., Yu et al. and Tuominen would result to “wherein forming encapsulant on the semiconductor die further includes forming the encapsulant to cover a plurality of sidewalls of the semiconductor die and cover a surface of the semiconductor die facing away from the adhesive layer and the insulating layer.” Regarding claim 25, Shen et al. discloses in Fig. 13B, paragraph [0040] grinding a portion of the encapsulant [70] to expose the surface of the semiconductor die [410]. Yu et al. discloses in Fig. 2E grinding a portion of the encapsulant [150] to expose the surface of the semiconductor die [120]. Regarding claim 26, Shen et al. discloses in Fig. 7-Fig. 8, paragraph [0029] singulating the bonding layer [30], and the encapsulant [70] forming respective sidewalls of the bonding layer [30], and the encapsulant [70], and wherein the respective sidewalls of the bonding layer [30], and the encapsulant [70] are coplanar with each other. Yu et al. and Tuominen suggests the bonding layer comprising the insulating layer and the adhesive layer. Thus, the combination of Shen et al., Yu et al. and Tuominen would result to singulating the insulating layer and the adhesive layer, and the encapsulant forming respective sidewalls of the insulating layer and the adhesive layer, and the encapsulant, and wherein the respective sidewalls of the insulating layer and the adhesive layer, and the encapsulant are coplanar with each other.” Response to Arguments Applicant’s arguments with respect to claims 7-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 18, 2023
Application Filed
Mar 02, 2026
Non-Final Rejection mailed — §103
May 22, 2026
Examiner Interview Summary
May 22, 2026
Applicant Interview (Telephonic)
May 27, 2026
Response Filed
Jun 15, 2026
Final Rejection mailed — §103 (current)

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Patent 12677539
DISPLAY DEVICE
3y 5m to grant Granted Jul 07, 2026
Patent 12660223
CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE
4y 11m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
45%
Grant Probability
59%
With Interview (+13.7%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 520 resolved cases by this examiner. Grant probability derived from career allowance rate.

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