DETAILED ACTION
This action is responsive to the following communication: the response filed 2/3/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-14 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-11, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (US 2021/0335433 ‒hereinafter Harada) in view of Cho et al. (US 2021/0343352 ‒hereinafter Cho).
Regarding claim 1, Harada discloses a memory device comprising:
a memory array (110; fig. 1); and
control logic (200; fig. 1), operatively coupled with the memory array (110), to perform operations comprising:
responsive to receiving a request to resume (“memory controller 200 transmits a resume command yyh to the semiconductor storage device 100” para 0098) a previously suspended (i.e. from suspend command xxh; fig. 5) memory access operation (“resume command yyh is a command for instructing the resumption of the process that was interrupted [i.e. previously suspended from suspend command xxh]” para 0098), initiating a program verify operation (“verification operation [V; fig. 5] scheduled to be executed in the program loop is executed after the resumption [yyh]” para 0098) on a memory cell (i.e. any memory cell transistor MT; fig. 2) of the memory array (110), wherein the memory cell is associated with the previously suspended memory access operation (“The interrupt operation includes, for example, the read operation and the write operation of writing 1-bit data to the memory cell transistor MT” para 0093);
determining whether the memory cell passes the program verify operation (“determines whether or not the write operation in each state is completed” para 0089);
and responsive to determining that the memory cell does not pass (i.e. fails) the program verify operation (“memory cell transistor MT that fails in the verification operation” para 0122):
identifying a program level group (memory cell transistors scheduled to be written to “A” state, i.e. program level group “A”; fig. 3, further para 0117) of a plurality of program level groups (i.e. program level groups “A”, “B”, “C”; fig. 3) with which the memory cell is associated (i.e. the memory cell transistors including memory cell transistor MT);
determining a resume program offset value (amount of increase DVPGM2 after resume program; para 0112, 0122) associated with the program level group (i.e. for programming level group “A”), wherein each of the plurality of program level groups (i.e. each program level groups “A”, “B”, “C”) has a different respective resume program offset value (i.e. amount of increase DVPGM2 or DVPGM1; fig. 7, 9A, 9C) comprising a voltage offset value (i.e. programming pulse with offset value DVPGM2; fig. 7); and
causing a programming pulse (programming pulse with offset value DVPGM2 is applied after RESUME; fig. 7) to be applied to the memory cell (MT) to resume the previously suspended memory access operation (fig. 5, 7), wherein a magnitude of the programming pulse is based on the negative voltage offset value (i.e. programming pulse with offset value DVPGM2) associated with the program level group (i.e. for programming level group “A”).
Harada does not expressly disclose comprising a negative voltage offset value; programming pulse is reduced based on the negative voltage offset value.
Cho discloses comprising a negative voltage offset value (a resume program offset value, i.e. after a resume tRES, includes third voltage ΔV3 having a negative value; para 0106, further para 0107); programming pulse (Vpgm; fig. 5-8) is reduced based on the negative voltage offset value (programming pulse is shown reduced after tRES, i.e. based on ΔV3 having a negative value; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Harada is modifiable as taught by Cho facilitating data accessing schemes by adjusting voltages of program operations to compensate for detected variations during the operation (para 0097 of Cho), which is common and well known in the art to secure the integrity of data storage.
Regarding claim 2, Harada discloses the memory device, wherein initiating the program verify operation (para 0077) on the memory cell comprises causing a read voltage (VREAD, i.e. AR, BR, CR; fig. 3) to be applied to the memory cell to determine a level of charge (a data level corresponds to a charge stored, i.e. read data for each level of charge; para 0056) stored at the memory cell (para 0050).
Regarding claim 3, Harada discloses the memory device, wherein determining whether the memory cell passes the program verify operation comprises determining whether the level of charge stored at the memory cell is greater than or equal to a threshold voltage level (para 0077, 0088-0089).
Regarding claim 4, Harada discloses the memory device, wherein identifying the program level group of the plurality of program level groups comprises: determining (ST90; fig. 6) a programming level (i.e. any of programming level of selected word line WL; fig. 7) of a plurality of programming levels (fig. 7) to which the memory cell was to be programmed (i.e. for programming level group “A”) as part of the previously suspended memory access operation (fig. 5, 7), wherein each of the plurality of program level groups (i.e. each program level groups “A”, “B”, “C”) is associated with one or more of the plurality of programming levels (fig. 7).
Regarding claim 6, Harada discloses the memory device, wherein the previously suspended memory access operation comprises a program operation ([P] Program Operation; fig. 5), and wherein the program operation was suspended for a period of time (i.e. during Interrupt Operation; fig. 5) in response to a request to suspend the program operation (xxh; fig. 5), and wherein a read operation was performed on the memory array during the period of time for which the program operation was suspended (para 0093, 0104).
Regarding claim 7, Harada discloses the memory device, wherein the control logic is to perform operations further comprising: responsive to determining that the memory cell passes the program verify operation (para 0089), resuming the previously suspended memory access operation (previously suspended memory access operation prior to suspend command xxh is resumed after verify [V]; fig. 5) based on stored progress information (para 0098) associated with the previously suspended memory access operation (fig. 5).
Regarding claim 8, Harada discloses a method comprising:
responsive to receiving a request to resume (“memory controller 200 transmits a resume command yyh to the semiconductor storage device 100” para 0098) a previously suspended (i.e. from suspend command xxh; fig. 5) memory access operation (“resume command yyh is a command for instructing the resumption of the process that was interrupted [i.e. previously suspended from suspend command xxh]” para 0098), initiating a program verify operation (“verification operation [V; fig. 5] scheduled to be executed in the program loop is executed after the resumption [yyh]” para 0098) on a memory cell (i.e. any memory cell transistor MT; fig. 2) of a memory array (110; fig. 1) of a memory device (100; fig. 1), wherein the memory cell is associated with the previously suspended memory access operation (“The interrupt operation includes, for example, the read operation and the write operation of writing 1-bit data to the memory cell transistor MT” para 0093);
determining whether the memory cell passes the program verify operation (“determines whether or not the write operation in each state is completed” para 0089);
and responsive to determining that the memory cell does not pass (i.e. fails) the program verify operation (“memory cell transistor MT that fails in the verification operation” para 0122):
identifying a program level group (memory cell transistors scheduled to be written to “A” state, i.e. program level group “A”; fig. 3, further para 0117) of a plurality of program level groups (i.e. program level groups “A”, “B”, “C”; fig. 3) with which the memory cell is associated (i.e. the memory cell transistors including memory cell transistor MT);
determining a resume program offset value (amount of increase DVPGM2 after resume program; para 0112, 0122) associated with the program level group (i.e. for programming level group “A”), wherein each of the plurality of program level groups (i.e. each program level groups “A”, “B”, “C”) has a different respective resume program offset value (i.e. amount of increase DVPGM2 or DVPGM1; fig. 7, 9A, 9C); and
causing a programming pulse (programming pulse with offset value DVPGM2 is applied after RESUME; fig. 7) to be applied to the memory cell (MT) to resume the previously suspended memory access operation (fig. 7), wherein a magnitude of the programming pulse is based on the voltage offset value (i.e. programming pulse with offset value DVPGM2; fig. 7) associated with the program level group (i.e. for programming level group “A”).
Harada does not expressly disclose comprising a negative voltage offset value; programming pulse is reduced based on the negative voltage offset value.
Cho discloses comprising a negative voltage offset value (a resume program offset value, i.e. after a resume tRES, includes third voltage ΔV3 having a negative value; para 0106, further para 0107); programming pulse (Vpgm; fig. 5-8) is reduced based on the negative voltage offset value (programming pulse is shown reduced after tRES, i.e. based on ΔV3 having a negative value; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Harada is modifiable as taught by Cho facilitating data accessing schemes by adjusting voltages of program operations to compensate for detected variations during the operation (para 0097 of Cho), which is common and well known in the art to secure the integrity of data storage.
Regarding claim 9, Harada discloses the method, wherein initiating the program verify operation (para 0077) on the memory cell comprises causing a read voltage (VREAD, i.e. AR, BR, CR; fig. 3) to be applied to the memory cell to determine a level of charge (a data level corresponds to a charge stored, i.e. read data for each level of charge; para 0056) stored at the memory cell (para 0050).
Regarding claim 10, Harada discloses the method, wherein determining whether the memory cell passes the program verify operation comprises determining whether the level of charge stored at the memory cell is greater than or equal to a threshold voltage level (para 0077, 0088-0089).
Regarding claim 11, Harada discloses the method, wherein identifying the program level group of the plurality of program level groups comprises: determining (ST90; fig. 6) a programming level (i.e. any of programming level of selected word line WL; fig. 7) of a plurality of programming levels (fig. 7) to which the memory cell was to be programmed (i.e. for programming level group “A”) as part of the previously suspended memory access operation (fig. 5, 7), wherein each of the plurality of program level groups (i.e. each program level groups “A”, “B”, “C”) is associated with one or more of the plurality of programming levels (fig. 7).
Regarding claim 13, Harada discloses the method, wherein the previously suspended memory access operation comprises a program operation ([P] Program Operation; fig. 5), and wherein the program operation was suspended for a period of time (i.e. during Interrupt Operation; fig. 5) in response to a request to suspend the program operation (xxh; fig. 5), and wherein a read operation was performed on the memory array during the period of time for which the program operation was suspended (para 0093, 0104).
Regarding claim 14, Harada discloses the method, further comprising: responsive to determining that the memory cell passes the program verify operation (para 0089), resuming the previously suspended memory access operation (previously suspended memory access operation prior to suspend command xxh is resumed after verify [V]; fig. 5) based on stored progress information (para 0098) associated with the previously suspended memory access operation (fig. 5).
Claim(s) 5, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (US 2021/0335433 ‒hereinafter Harada) in view of Cho et al. (US 2021/0343352 ‒hereinafter Cho), and further in view of Hyun et al. (US 2016/0210050 ‒hereinafter Hyun).
Regarding claim 5, Harada as modified does not expressly disclose the memory device, wherein determining the resume program offset value associated with the program level group comprises accessing a corresponding entry of a plurality of entries in a data structure, wherein each of the plurality of entries is associated with a respective program level group of the plurality of program level groups and comprises a respective resume program offset value.
Hyun discloses determining the resume program offset value (ΔVpr corresponding to a resume after suspend command FFh at operation step 525; fig. 5) associated with the program level group (any program loop 1-6; fig. 5) comprises accessing a corresponding entry of a plurality of entries (entries corresponding to each program loop 1-6 and associated operation steps; fig. 5) in a data structure (fig. 5), wherein each of the plurality of entries (i.e. each program loop entry) is associated with a respective program level group (loop 1-6) of the plurality of program level groups and comprises a respective resume program offset value (i.e. 2 ΔVpr, 3 ΔVpr, 4 ΔVpr, 5 ΔVpr; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Harada is further modifiable as taught by Hyun for the purpose of facilitating program suspend/resume by allowing additional memory access operations to be processed, which may decrease a latency for the additional operations and reduce stress and wear on the device (para 0033 of Hyun).
Regarding claim 12, Harada as modified does not expressly disclose the method, wherein determining the resume program offset value associated with the program level group comprises accessing a corresponding entry of a plurality of entries in a data structure, wherein each of the plurality of entries is associated with a respective program level group of the plurality of program level groups and comprises a respective resume program offset value.
Hyun discloses determining the resume program offset value (ΔVpr corresponding to a resume after suspend command FFh at operation step 525; fig. 5) associated with the program level group (any program loop 1-6; fig. 5) comprises accessing a corresponding entry of a plurality of entries (entries corresponding to each program loop 1-6 and associated operation steps; fig. 5) in a data structure (fig. 5), wherein each of the plurality of entries (i.e. each program loop entry) is associated with a respective program level group (loop 1-6) of the plurality of program level groups and comprises a respective resume program offset value (i.e. 2 ΔVpr, 3 ΔVpr, 4 ΔVpr, 5 ΔVpr; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Harada is further modifiable as taught by Hyun for the purpose of facilitating program suspend/resume by allowing additional memory access operations to be processed, which may decrease a latency for the additional operations and reduce stress and wear on the device (para 0033 of Hyun).
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______
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