DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/16/2024 is being considered by the examiner.
Drawings
The drawings submitted on 10/18/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US 20210013210 A1).
Regarding claim 1, Lee discloses a memory cell structure (bottom left MC) comprising:
a vertical bit line (BL/120); ([0044], Fig. 1A and 2A)
an Insulator (116) surrounding a first portion of vertical bit line (BL/120); ([0094], Fig. 2A)
a continuous semiconductor layer (VA/115) surrounding the insulator (116) and a second portion of the vertical bit line (BL); ([0030], [0059], Fig. 1B and 2A)
an extended portion of conductor material (114) surrounding the continuous semiconductor layer (VA/115) ([0055], Fig. 2A)
a first dielectric layer (113) surrounding extended portion of conductor material (114); ([0055], Fig.2A)
a first conductor layer (112) surrounding the first dielectric layer (113); ([0055], Fig.2A)
a second conductor layer (130) surrounding the first conductor layer (112); ([0058], Fig. 2A)
a second dielectric layer (127) on a top surface (top side surface of second conductor 130 of bottom left cell MC) of the first and second conductor layers (112/130); ([0046], Fig. 2A)
a third dielectric layer (127) on a bottom surface (bottom side surface of second conductor 130 of bottom left cell MC) of the first and second conductor layers (112/130); (Fig. 2A)
a first gate (128) on a top surface of the second dielectric layer (127); ([0046], Fig. 2A) and
a second gate (128) on a bottom surface of the third dielectric layer (127). ([0046], Fig. 2A)
Regarding claim 2, Lee discloses a memory cell structure (bottom left MC) comprising:
a vertical bit line (BL/120); ([0044], Fig. 1A and 2A)
an Insulator (116) surrounding a first portion of vertical bit line (BL/120); ([0094], Fig. 2A)
a continuous semiconductor layer (VA/115) surrounding the insulator (116) and a second portion of the vertical bit line (BL); ([0030], [0059], Fig. 1B and 2A)
an extended portion of conductor material (114) surrounding a first portion of a side surface of the continuous semiconductor layer (VA/115); ([0055], Fig. 2A)
a first dielectric layer (113) surrounding the extended portion of conductor material (114) and a second portion of the side surface of the continuous semiconductor layer (VA/115); ([0055], Fig.2A)
a first conductor layer (112) surrounding the first dielectric layer (113); ([0055], Fig.2A)
a second dielectric layer (127) above a top surface of the first conductor layer (112); (Fig. 2A)
a third dielectric layer (127) below a bottom surface of the first conductor layer (112); (Fig. 2A)
a second conductor layer (128) on a top surface of the first dielectric layer (113); (Fig. 2A) and
a third conductor layer (128) on a bottom surface of the third dielectric layer (127). (Fig. 2A)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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