DETAILED ACTION
This office action is in response to the application filed 10/18/2023.
Currently, claims 1-3 are pending.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: 3D MEMORY CELLS AND ARRAY STRUCTURES WITH CONDUCTOR CORES.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Ishihara et al. (US 8,455,941).
Pertaining to claim 1, Ishihara shows, with reference to FIG. 5A-B, a 3D memory cell structure, comprising:
a vertical conductor core (PBG);
an insulator (49) surrounding the vertical conductor core;
a semiconductor layer (SP) surrounding the insulator;
charge trapping layers (42, 48, 43) surrounding the semiconductor layer; and
a word line layer (61) surrounding at least a portion of the charge trapping layers.
Pertaining to claim 2, Ishihara shows the charge trapping layers comprise oxide-nitride-oxide (ONO) layers (col. 11, lines 43-57).
Allowable Subject Matter
Claim 3 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: While not nearly as common as 3D memory structures having a vertical insulating core, 3D memory structures having a vertical conductor core are known in the art, as disclosed by Ishihara, for example. However, the prior art does not teach or suggest a 3D memory string comprising a bit line and first and second sub-strings, each sub-string having a conductor core and a drain select gate that controls when voltage on the bit line is applied to the respective sub-string, and wherein a landing pad connects the conductor cores of the first and second sub-strings. Thus, claim 3 is found to be allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamazaki discloses a 3D memory structure having a vertical conductor core.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL LUKE/Primary Examiner, Art Unit 2896
Prosecution Insights