/2023DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al (US Publication No. 20070030610) in view of Zhao et al (US Publication No. 20180026440).
Regarding claim 1, Ker discloses a semiconductor device (i.e., such as semiconductor device; see for example fig. 3, para. [0018]- [0022]), comprising: a first resistance-capacitance (RC) timer circuit (i.e., such as first resistance-capacitance (RC) timer circuit (R1, C1); see for example fig. 3, para. [0018]- [0022]), coupled between a first power supply voltage (i.e., such as first power supply voltage (Reg 3.3V); see for example fig. 3, para. [0018]- [0022]) and a reference voltage (i.e., such as reference voltage Vss; see for example fig. 3, para. [0018]- [0022]); a second RC timer circuit (i.e., such as second RC timer circuit (C2, C3, R2); see for example fig. 3, para. [0018]- [0022]), coupled between a second power supply voltage (i.e., such as second power supply voltage (Reg 5V); see for example fig. 3, para. [0018]- [0022]) and the reference voltage (i.e., such as reference voltage Vss; see for example fig. 3, para. [0018]- [0022]), wherein the second power supply voltage (i.e., such as second power supply voltage (Reg 5V); see for example fig. 3, para. [0018]- [0022]) is higher (i.e., such as 5 > 3.3; see for example fig. 3, para. [0018]- [0022]) than the first power supply voltage (i.e., such as first power supply voltage (Reg 3.3V); see for example fig. 3, para. [0018]- [0022]); a voltage pull-down circuit (i.e., such as voltage pull-down circuit N3; see for example fig. 3, para. [0018]- [0022]), coupled between the first RC timer circuit (i.e., such as first resistance-capacitance (RC) timer circuit (R1, C1); see for example fig. 3, para. [0018]- [0022]) and the second RC timer circuit (i.e., such as second RC timer circuit (C2, C3, R2); see for example fig. 3, para. [0018]- [0022]); a discharge circuit (i.e., such as discharge circuit 20; see for example fig. 3, para. [0018]- [0022]), coupled between the second power supply voltage (i.e., such as second power supply voltage (Reg 5V; see for example fig. 3, para. [0018]- [0022]) and the reference voltage (i.e., such as reference voltage Vss; see for example fig. 3, para. [0018]- [0022]).
Ker does not explicitly disclose a voltage pull-up circuit, coupled between the second power supply voltage and the reference voltage through a first resistor; and a discharge control circuit, coupled between a third node and the reference voltage, and configured to control the discharge circuit using a first voltage generated by the first RC timer circuit.
Zhao discloses an ESD apparatus (i.e., such as high voltage clamp 50; see for example fig. 2, para. [0055]- [0078]); wherein a voltage pull-up circuit (i.e., such as voltage pull-up circuit 42; see for example fig. 2, para. [0055]- [0078]), coupled between the second power supply voltage (i.e., such as second power supply voltage VHV; see for example fig. 2, para. [0055]- [0078]) and the reference voltage (i.e., such as reference voltage VSS; see for example fig. 2, para. [0055]- [0078]) through a first resistor (i.e., such as first resistor 43; see for example fig. 2, para. [0055]- [0078]); and a discharge control circuit (i.e., such as discharge control circuit 41; see for example fig. 2, para. [0055]- [0078]), coupled between a third node (i.e., such as third node as of the gate of the clamp transistor NMOS 23; see for example fig. 2, para. [0055]- [0078]) and the reference voltage (i.e., such as reference voltage VSS; see for example fig. 2, para. [0055]- [0078]), and configured to control (i.e., such as configured to control; see for example fig. 2, para. [0055]- [0078]) the discharge circuit (i.e., such as discharge circuit clamp transistor NMOS 23; see for example fig. 2, para. [0055]- [0078]) using a first voltage (i.e., such as first voltage VTRIG; see for example fig. 2, para. [0055]- [0078]) generated by (i.e., such as generated by TRIGGER CKT 31; see for example fig. 2, para. [0055]- [0078]) the first RC timer circuit (i.e., such as first RC timer circuit 31; see for example fig. 2, para. [0055]- [0078]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the transistors and the resistor devices in Ker, as taught by Zhao, as it provides the advantage of optimizing the circuit design towards preventing false triggering during normal operation and ensuring uniform activation to prevent the ESD device from burning out.
Allowable Subject Matter
Claims 2-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Ker in view of Zhao teaches the invention set forth above. However, neither Ker nor Zhao particularly teaches wherein the first RC timer circuit comprises a second resistor and a first capacitor, wherein the second resistor is coupled between the first power supply voltage and a first node, and the first capacitor is coupled between the first node and the reference voltage, and the first voltage is generated at the first node.
Hence claim 2 will be deemed allowable if rewritten in an independent form.
Claims 3-5 and 11-14 depend on objected claim 2, consequently claims 3-5 and 11-14 will also be deemed allowable.
Regarding claim 6, Ker in view of Zhao teaches the invention set forth above. However, neither Ker nor Zhao particularly teaches wherein the discharge circuit, the voltage pull-down circuit, the discharge control circuit, and the voltage pull-up circuit are implemented using a first transistor, a second transistor, a third transistor, and a fourth transistor.
Hence claim 6 will be deemed allowable if rewritten in an independent form.
Claims 7-10 depend on objected claim 6, consequently claims 7-10 will also be deemed allowable.
Claims 21-26 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 21, Ker et al (US Publication No. 20070030610) in view of Zhao et al (US Publication No. 20180026440) substantially teaches the claim limitations as indicated in claim 1. However, neither Ker nor Zhao teaches or suggests a semiconductor device, comprising: a first resistance-capacitance (RC) timer circuit, coupled between a first power rail for a first power supply voltage and a reference rail; a second RC timer circuit, coupled between a second power rail for a second power supply voltage and the reference rail, wherein the second power supply voltage is higher than the first power supply voltage; a first transistor, coupled between the first RC timer circuit and the second RC timer circuit; a second transistor, coupled between the second power rail and the reference rail through a first resistor; a third transistor, coupled between the second power rail and the reference rail; and a fourth transistor, coupled between a first node and the reference rail, and configured to control the discharge circuit based on a first voltage generated by the first RC timer circuit, wherein a width of the first transistor is greater than that of the second transistor, the third transistor, and the fourth transistor.
Claims 22-23 are allowed, as they depend on allowed claim 21.
Regarding claim 24, Ker et al (US Publication No. 20070030610) in view of Zhao et al (US Publication No. 20180026440) substantially teaches the claim limitations as indicated in claim 1. However, neither Ker nor Zhao teaches or suggests a semiconductor device, comprising: a first resistance-capacitance (RC) timer circuit, coupled between a first power rail for a first power supply voltage and a reference rail; a second RC timer circuit, coupled between a second power rail for a second power supply voltage and the reference rail, wherein the second power supply voltage is higher than the first power supply voltage; a first first-type transistor, coupled between the first RC timer circuit and the second RC timer circuit; a first second-type transistor, coupled between the second power supply voltage and the reference rail through a first resistor; a second second-type transistor, coupled between the second power rail and the reference rail; and a second first-type transistor, coupled between a first node and the reference rail, and configured to control the discharge circuit based on a first voltage generated by the first RC timer circuit, wherein the first second-type transistor and the second second-type transistor operate with the first power supply voltage, and the first second-type transistor and the second second-type transistor operate with the second power supply voltage.
Claims 25-26 are allowed, as they depend on allowed claim 24.
Claims 15-20 are cancelled.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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