DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon applications filed in the COUNTRY OF KOREA on 03/24/2023 and 04/28/2023.
Election/Restrictions
Applicant's election without traverse of “Invention I including Species Groups A1 and B1 (Claims 1-11)” in the reply filed on 02/20/2026, is acknowledged.
Claims 12-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “a first wiring line portion comprising a first minimum width of 10 µm or less in the horizontal direction” does not particularly point out and distinctly claim a minimum width, since the minimum width range continuous opened to any size lesser than 10 µm.
Application will be examined with Claim 3 being best interpreted by the Examiner in the following manner:
The semiconductor package of claim 1, wherein the plurality of outermost wiring lines comprise a first wiring line portion comprising a first minimum width of 10 μm in the horizontal direction, and a second wiring line portion comprising a second minimum width that is greater than 10 μm in the horizontal direction,
and wherein the respective surface roughness of the first wiring line portion is 0.1 μm or less, and the respective surface roughness of the second wiring line portion is greater than 0.1 μm and less than or equal to about 0.6 μm.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being obvious over US 2017/0250170 A1; Yu et al.; 08/2017; (“170”) in view of US 2026/0026371 A1; Kim et al.; 01/2026; (“371”).
Regarding Claim 1. 170 teaches in Fig. 18 about a semiconductor package comprising:
a first package unit comprising a semiconductor chip (lower semiconductor package comprising semiconductor chip item 102); and
a redistribution structure on the first package unit (item 412),
wherein the redistribution structure comprises a plurality of wiring lines and a plurality of insulating layers on the plurality of wiring lines (“redistribution structure including a one or more conductive lines … in one or more insulating layers”, [0048], Ln 2-3), wherein the plurality of wiring lines comprise a first subset including a plurality of outermost wiring lines (outermost wiring line of redistribution structure item 412) and a second subset (other wiring lines not including the outermost wiring line of redistribution structure item 412),
wherein a vertical distance between the plurality of outermost wiring lines and the first package unit is greater than a vertical distance between the second subset of the plurality of wiring lines and the first package unit (vertical distance between the outermost wiring line of item 412 and item 102 is greater than a vertical distance between the other wiring lines of item 412 and item 102).
170 does not teach about a semiconductor package comprising:
a respective surface roughness of each of the plurality of outermost wiring lines is different, and
the respective surface roughness of each of the plurality of outermost wiring lines is based on a respective width of each of the plurality of outermost wiring lines in a horizontal direction.
371 teaches in Fig. 28 about a semiconductor memory device, comprising:
a respective surface roughness of each of the plurality of bottom most wiring lines is on average the same (“average surface roughness (Ra) applied to an interface between an insulating layer and an electrode part.”, [0010], Ln. 3-4).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the average surface roughness of the outermost wiring lines of 371 to improve the interface adhesion between the insulating layers and the wiring lines specially for large area interfaces in 170 as taught by 371 in Fig. 28 and [0010], Ln. 3-4.
Allowable Subject Matter
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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