DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF JAPAN on 10/20/2022.
Election/Restrictions
Applicant's election with traverse of “Species B (claims 1-20)” in the reply filed on 02/24/2026, is acknowledged. Applicant’s arguments are persuasive regarding the species restriction; therefore, the species restriction is hereby withdrawn and claims 1-20 will be examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3 and 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Dependent claims 3 and 7 include the limitation “wherein the first via conductors and the second via conductors are formed in the first via holes” which contradicts the following limitation of claim 1 “forming a plurality of first via conductors in the first via holes formed in the second insulating layer, respectively; and forming a plurality of second via conductors in the second via holes formed in the second insulating layer, respectively”.
Application will be examined with claims 3 and 7 being best interpreted by the Examiner in the following manner:
wherein the first via conductors and the second via conductors are formed in a same process.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3,5-7,9-10,12-13,16 and 18-20 are rejected under 35 U.S.C. 103 as being obvious over US 2019/0267327 A1; Aoki; 08/2019; (“327”).
Regarding Claim 1. 327 teaches in Figs. 5B and 5C about a method for manufacturing a wiring substrate, comprising:
forming a plurality of conductor pads (Fig. 5B, items 16b) on a surface of an insulating layer (Fig. 5B, items 16b are formed on the top surface of grouped insulating layer items 13 and 15, “the insulating layer 15 may be equal in material and thickness to, for example, the insulating layer 13”, [0028], 3-4);
positioning, on or in the insulating layer, an electronic component (Fig 5B, item 30 is positioned on or in the insulating layer) having a plurality of electrode pads (Fig. 5B, item 30 has a plurality of electrode pad items 32a);
forming a second insulating layer (Fig. 5B, item 17) on the insulating layer such that the second insulating layer covers the surface of the insulating layer, the conductor pads and the electronic component (Fig. 5B, item 17 is formed on and covers the surface of the insulating layer, items 16b and item 30;
forming a plurality of first via holes in the second insulating layer (Fig. 5B, first via hole items 17x are formed in item 17) such that the first via holes expose the conductor pads formed on the surface of the insulating layer (Fig. 5B, items 17x expose items 16b formed on the top-surface of grouped items 13 and 15), respectively;
forming a plurality of second via holes in the second insulating layer (Fig. 5B, second via hole items 17y are formed in item 17) such that the second via holes expose the electrode pads of the electronic component positioned on or in the insulating layer (Fig. 5B, items 17y expose items 32a of item 30 positioned on or in the insulating layer), respectively;
applying a single desmear treatment to the second insulating layer such that residues are removed from the first and second via holes formed in the second insulating layer (Fig. 5B, “after formation of the via holes 17x, 17y, … it is preferable to perform a desmear process to remove residual resin”, [0062], Ln. 10-13);
forming a plurality of first via conductors in the first via holes formed in the second insulating layer (Fig. 5C, items 18a connecting to items 16b, are formed in items 17x), respectively; and
forming a plurality of second via conductors in the second via holes formed in the second insulating layer (Fig. 5C, items 18a connecting to items 32a, are formed in items 17y).
327 does not teach about a method for manufacturing a wiring substrate, comprising:
applying a first desmear treatment to the second insulating layer such that residues are removed from the first via holes formed in the second insulating layer;
forming a plurality of second via holes in the second insulating layer after the first desmear treatment such that the second via holes expose the electrode pads of the electronic component positioned on or in the insulating layer, respectively; and
applying a second desmear treatment to the second insulating layer such that residues are removed from the second via holes formed in the second insulating layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to separate the formation of two via conductor hole types (within the same insulating layer) into two different steps of the same process (including the respective hole desmearing for each type of hole via conductor forming step), since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). See MPEP 2144.04.
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Fig. 5C, annotated by Examiner from Aoki, “327”
Regarding Claim 2. 327 teaches in Fig. 5B about a method for manufacturing a wiring substrate, wherein a single desmear treatment is applied to the second insulating layer such that residues are removed from the first and second via holes formed in the second insulating layer (Fig. 5B, “after formation of the via holes 17x, 17y, … it is preferable to perform a desmear process to remove residual resin”, [0062], Ln. 10-13).
327 does not teach about a method for manufacturing a wiring substrate, wherein the second desmear treatment is applied such that a processing time of the second desmear treatment is shorter than a processing time of the first desmear treatment.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to separate the formation of two via conductor hole types (within the same insulating layer) into two different steps of the same process (including the respective hole desmearing for each type of hole via conductor forming step); furthermore, it would be expected that the second desmearing treatment would be shorter than the first desmearing treatment because the via holes 17x are less deep than the via holes 17y, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 129 USPQ 348, 349 (CCPA 1961). See MPEP 2144.04.
Regarding Claim 3. 327 teaches in Fig. 5C about a method for manufacturing a wiring substrate, wherein the first via conductors and the second via conductors are formed in a same process (“the wiring layer 18 is formed … by the same process”, [0063], Ln. 1-3).
Regarding Claim 5. 327 teaches in Fig. 5B about a method for manufacturing a wiring substrate, wherein the forming of the first and second via holes includes irradiating laser upon the second insulating layer such that irradiation of the laser forms the first and second via holes in the second insulating layer (“via holes 17x, 17y, … may be formed by, for example, laser processing”, [0062], Ln. 8-10).
327 does not teach about a method for manufacturing a wiring substrate, wherein the forming of the first via holes includes irradiating laser upon the second insulating layer such that irradiation of the laser forms the first via holes in the second insulating layer, and the forming of the second via holes includes irradiating laser upon the second insulating layer at a wavelength that is shorter than a wavelength of the laser for the forming of the first via holes such that the irradiation of the laser forms the second via holes in the second insulating layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to experiment with different laser wavelengths for the formation of the first and second via holes with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding Claim 6. 327 teaches in Fig. 5B about a method for manufacturing a wiring substrate, wherein the electrode pads of the electronic component have an inter-pad distance that is shorter than an inter-pad distance of the conductor pads formed on the surface of the insulating layer (horizontal distance between items 32a is shorter than distance between items 16b corresponding to via holes 17x).
Regarding Claim 7. Same as claim 3.
Regarding Claim 9,12,18 and 20. Same as claim 5.
Regarding Claim 10,13,16 and 19. Same as claim 6.
Claims 4,8,11,14-15 and 17 are rejected under 35 U.S.C. 103 as being obvious over US 2019/0267327 A1; Aoki; 08/2019; (“327”) in view of US 2024/0006285 A1; Yang et al.; 01/2024; (“285”).
Regarding Claim 4. 327 teaches in Fig. 5C about a method for manufacturing a wiring substrate, comprising:
no coating film on the plurality of conductor pads and the plurality of electrode pads such that the coating film covers surfaces of the conductor pads and the electrode pads.
327 does not teach about a semiconductor memory device, comprising:
forming a coating film on the plurality of conductor pads and the plurality of electrode pads such that the coating film covers surfaces of the conductor pads and the electrode pads.
285 teaches in Fig. 2 about a method for manufacturing a wiring substrate, comprising:
forming a coating film (item 218) on the plurality of conductor pads and the plurality of electrode pads such that the coating film covers surfaces of the conductor pads and the electrode pads (item 218 coats items 210 and 210a).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the coating film of 285 to promote or improve adhesion between the second insulation layer and the conductor or electrode pads in 327 as taught by 285 in Fig. 2 and [0036], Ln. 1-2.
Regarding Claims 8,11 and 17. Same as claim 4.
Regarding Claim 14. Same as claim 5.
Regarding Claim 15. Same as claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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