DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This Office Action is responsive to communication filed on 9/15/2025.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Abuku (US4870288A) in view of Son (US6421456B1) (hereinafter – “Abuku-Son”).
Regarding claim 18
Abuku teaches:
manually performing leveling processes Col. 1, ll. 49: “first wafer is manually aligned”); and
saving patterns of the first wafer into a database (Col. 1, ll. 49-50: “first wafer is manually aligned, then some data are memorized after the alignment is accomplished”); and
automatically performing leveling processes (Col. 1, ll. 51-52: “thereafter, the next and subsequent wafers are automatically aligned on the basis of the data”, implied is that the next and subsequent wafers are identical to the first wafer so the next and subsequent wafers can be automatically aligned on the basis of the data of the first wafer).
Abuku is not relied on for dicing the first or second wafer. Abuku is also not relied on for dicing marks.
However, Son in analogous art teaches:
dicing a first wafer (Col. 3, ll. 15-18: “preparation method comprises formation of standard recognition marks on the wafer and sawing the wafer by using the standard recognition marks for alignment of the wafer”) comprising:
Col. 4, ll. 23-27: “recognition mark 40 is formed on each crossing point where a vertical scribe line 34 intersects a horizontal scribe line 36. The recognition mark 40 is used as a reference pattern for inspecting wafer alignment”)
dicing a second wafer identical to the first wafer, wherein the dicing the second wafer comprises:
automatically finding dicing marks on the second wafer using patterns of the first wafer saved in the database (Col. 5, ll. 4-8: “camera 76 recognizes recognition mark 40 on wafer 30. Then, in step 48, control unit 78 drives wafer aligning stage 72 and, according to the data obtained from recognition mark 40, aligns one of vertical or horizontal scribe lines 34 or 36 under saw blade 74. After finishing wafer alignment (step 58), saw blade 74 cuts wafer”).
Abuku and Son are analogous art to the claimed invention because they are from the same field of semiconductor die manufacturing. Before the effective filing date of the claimed invention, it would have been obvious to one or ordinary skill in the art to apply the teachings of Son to the teachings of Abuku such that Son’s recognition marks could be used with Abuku’s leveling process for the purposes of providing a reference point off which to level the wafer so that the kerf centers align with the dicing mechanism. Based on the above, this is an example of “combining prior art elements according to known methods to yield predictable results.” MPEP 2143.
Regarding claim 20
Abuku-Son teaches the elements of claim 18 as outlined above.
Son also teaches wherein the patterns of the first wafer saved in the database comprise a pattern of a crossroad (Fig. 5 shows a crossroad pattern).
Claim 19 is rejected under 35 U.S.C. as being unpatentable over Abuku-Son in view of Takagi (US20220288738A1).Regarding claim 19
Abuku-Son teaches the elements of claim 18 as outlined above.
Abuku-Son are not relied on for wherein the patterns of the first wafer saved in the database comprise a pattern of an L-mark.
However, Takagi in an analogous art does teach this claim limitation ([0022]: “device
16 in the present embodiment has an L-shaped characteristic pattern 18 as depicted in FIG. 3”).
Takagi is analogous art to the claimed invention because they are from the same field of semiconductor die manufacturing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to apply the teachings of Takagi to the teachings of Abuku-Son such that Takagi’s L-shaped pattern could be used with Abuku-Son’s method for the purposes of indicating a kerf intersection.
Allowable Subject Matter
Claims 1-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Narita (US20170148700A1) teaches a wafer dicing method including forming an optically readable mark, having at least a specific shape or pattern, to be used as an alignment mark for a kerf region.
James (US20180233410A1) teaches a multi-pattern wafer dicing method including singulating dies of various sizes from a wafer, wherein the pattern is downloaded to a laser groove dicing system to be used as an overlay for the dicing process.
Takagi (US20220288738A1) teaches a wafer dicing method including target pattern acquisition, target pattern storage, and target pattern matching wherein the wafer is aligned to the pattern prior to dicing.
Holcman (US20020042153A1) teaches a wafer dicing method including determining the location of kerf lines relative to the geometrical center of the wafer.
Fujimori (US20150087088A1) teaches a wafer dicing method including identifying dicing marks on a wafer, determining kerf centers on the wafer from the dicing marks, and dicing the wafer.
The prior art of record does not teach or suggest, either individually or in combination, including a plurality of dicing marks wherein those dicing marks are used to measure a first-channel die pitch of a wafer according to a pitch of two adjacent dicing marks.
Specifically, the prior art of record does not teach or suggest, either individually or in combination:
forming a database;
finding a plurality of dicing marks on a first wafer, wherein patterns of the plurality of dicing marks match a first pattern in the database;
measuring a first-channel die pitch of the first wafer according to a first pitch of adjacent two of the plurality of dicing marks;
determining kerf centers of he first wafer based on the plurality of dicing marks, wherein the measuring the first-channel die pitch and determining the kerf centers are performed on a same-wafer holding platform; and
dicing the first wafer into a plurality of dies, wherein the dicing is performed aligning to the kerf centers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen, F., et al. (“Automated vision positioning system for dicing semiconductor chips using improved template matching method”, published 10/19/2018. Retrieved from https://link.springer.com/article/10.1007/s00170-018-2845-5. Accessed 1/26/2026.) teaches an on-machine vision positioning system to automatically determine the dicing position through the image recognition technology.
Wang, Y., et al. (“An automatic detection method for cutting path of chips in a wafer”, published 12/26/2022. Retrieved from https://www.mdpi.com/2072-666X/14/1/59. Accessed on 1/26/2026.) teaches varying illumination levels to determine cutting paths of a wafer to be singulated.
Buera, M. V. S., et al. (“Pattern recognition system program advancement to compensate strip expansion on 1-map strips” published 5/21/2021. Retrieved from https://journaljerr.com/index.php/JERR/article/view/481/963. Accessed on 1/27/2026.) teaches a pattern recognition system wherein pattern recognition system points are used to calculate the alignment of a kerf street on a wafer to be singulated.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael V Farina whose telephone number is (571)272-4982. The examiner can normally be reached Mon-Thu 8:00-6:00 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached at (571) 272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.V.F./Examiner, Art Unit 2115
/KAMINI S SHAH/Supervisory Patent Examiner, Art Unit 2115