DETAILED ACTION
This office action is in response to the election filed 6/23/2026.
Currently, claims 1-20 are pending. Of these, claims 5 and 18 have been withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of Species I is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 1 is objected to because “wherein the first connection wirings and the second connection wirings” (lines 8-9) is only a portion of a clause. It does not make sense without further description.
Claims 19 and 20 are objected to because there is no space preceding the reference numerals within parentheses.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12, 16 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation “spaced apart from the first and second semiconductor chips based on the third direction”. It is not clear what is meant by “based on”, which implies a determination being made depending on conditions. For purposes of examination, it is understood to mean that the direction in which the chips are spaced is the third direction.
Claim 11 recites the limitation “the first connection wiring” in line 1. It is not clear to which, if any, of the first connection wirings recited in claim 1 this limitation refers. The same is true for “the second connection wiring” recited in line 5. This also occurs in claim 16.
Claim 19 recites the limitation “first … to third connection wirings … electrically connected to the display panel and the driving printed circuit board”. This reads as if there are connection wirings that connect to both the display panel and the driving printed circuit board, which does not appear to be supported by the disclosure. Thus, the limitation is not clear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-14, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Koo et al. (US 2021/0074622) in view of Chung et al. (US 10,304,764).
Pertaining to claim 1, Koo shows, with reference to FIG. 5, a chip on film package comprising:
a film substrate (110) including an upper layer (110T) extending in a first direction (+y) and a second direction (-y) opposite to each other and a lower layer (110B) facing the upper layer, and having a cutting line (101) formed thereon;
first and second semiconductor chips (any two of 200, 301, 302) disposed on the upper layer within an area of the cutting line;
first connection wirings (121) connected to the first semiconductor chip and second connection wirings (121) connected to the second semiconductor chip (FIG. 5C-E); and
a test pad (141 or 142) connected to at least one of the first and second connection wirings and disposed on the lower layer.
Pertaining to claim 13, Koo shows a chip on film package comprising:
a film substrate (110) including an upper layer (110T) and a lower layer (110B) facing each other and having a cutting line (101) formed thereon;
first (530) and second (430) connection wirings electrically connected to a display panel (500) and a driving printed circuit board (400), respectively (FIG. 1);
first to third semiconductor chips (200, 301, 302) electrically connected to the first and second connection wirings, on the upper layer of the film substrate;
a test pad (141, 142) electrically connected to at least one of the first and second connection wirings; and
a test pad connection via (123) penetrating through the film substrate,
wherein the test pad is disposed on the lower layer of the film substrate.
Pertaining to claim 19, Koo shows a display apparatus comprising:
a chip on film package including a film substrate (110) including an upper layer (110T) extending in first (+y) and second (-y) directions opposite to each other and a third (x) direction crossing each of the first and second directions and a lower layer (110B) facing the upper layer and having a cutting line (101) formed thereon;
a display panel (500) formed on a first side of the chip on film package; and
a driving printed circuit board (400) formed on a second side of the chip on film package,
wherein the chip on film package includes:
first to third semiconductor chips (200, 301, 302) disposed on the upper layer within an area of the cutting line;
first, second, and third connection wirings (430, 530) connected to the first to third semiconductor chips, respectively, and electrically connected to the display panel and the driving printed circuit board;
connection vias (123) penetrating through the film substrate and connected to the first to third connection wirings; and
a test pad (141, 142) connected to at least one of the first to third connection wirings through the connection vias and disposed on the lower layer.
Koo fails to show the test pad is within the area of the cutting line.
However, Chung teaches in e.g. FIG. 3A-B that, for a similar chip on film package, while some test pads 337 are located outside the cutting line area CL1/CL2, other pads 313(a/b) and 323(a/b) that are located within the area of the cutting line also function as test pads (col. 8, line 60 – col. 9, line 4).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Koo such that some of the pads within the cutting line area function as a test pads, as taught by Chung, with the motivation that the size of the film package may be reduced (col. 9, lines 3-4).
Pertaining to claims 2 and 14, in the case that Koo is modified such that e.g. 131 acts as the test pad, Koo shows the test pad is disposed between the first and second semiconductor chips (FIG. 5A-B).
Pertaining to claims 4 and 17, Chung teaches a test pad connection via (315 or 322) penetrating through the film substrate and electrically connecting the test pad and at least one of the first and second connection wirings to each other.
Pertaining to claim 6, Chung teaches the test pad is connected to the test pad connection via through a test pad connection wiring (321).
Pertaining to claims 7-8, Chung teaches the shape may be circular or polygonal (FIG. 3A).
Pertaining to claim 9, the specification contains no disclosure of either the critical nature of the claimed dimensions or of any unexpected results arising there from. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in the claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1515, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Pertaining to claim 10, Koo shows the upper layer further extends in a third (x) direction crossing each of the first and second directions, and the chip on film package further comprises a third semiconductor chip (e.g. 302) disposed on the upper layer and disposed to be spaced apart from the first (e.g. 301) and second (e.g. 200) semiconductor chips based on the third direction.
Pertaining to claims 11 and 16, Koo shows the first connection wiring includes a first-first connection wiring connected to the first semiconductor chip, a first-second connection wiring connected to the second semiconductor chip, and a first-third connection wiring connected to the third semiconductor chip, and the second connection wiring includes a second-first connection wiring connected to the first semiconductor chip, a second-second connection wiring connected to the second semiconductor chip, and a second-third connection wiring connected to the third semiconductor chip (FIG. 5A).
Pertaining to claims 12 and 20, Koo shows the first-first and first-second connection wirings are disposed on the upper layer, and the first-third connection wiring is disposed on the lower layer through a through-via penetrating through the film substrate (FIG. 5A-B, E).
Allowable Subject Matter
Claims 3 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Pertaining to claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including the first connection wiring being electrically connected to a display panel, the second connection wiring being electrically connected to a driving printed circuit board, and the test pad being disposed between the first semiconductor chip and the driving printed circuit board. Koo shows only pads 150 are located within the cutting line area and between the first chip and the driving printed circuit board (see e.g. FIG. 1-2). However, these pads are formed on the same surface (110T) as the semiconductor chips in every embodiment, and therefore cannot be considered to be the claimed test pad, which must be disposed on the lower layer facing the upper layer on which the chips are formed, as recited in claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Won et al. (US 10,559,526) discloses a chip on film package with a rest pad on the bottom of the flexible substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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