CTNF 18/490,622 CTNF 90369 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Regarding independent claims the limitations determines a first power, as drafted, recites functions that, under its broadest reasonable interpretation, covers a function that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitations as cited above as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. Thus, these limitation falls within the “Mental Processes” grouping of abstract ideas under Prong 1. Under Prong 2, this judicial exception is not integrated into a practical application. The claim recites the following additional limitations: compute node, hardware entities, virtual machines. The additional elements are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or mere computer components, MPEP 2106.05(f). Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of compute node, hardware entities, virtual machines, amount to no more than mere instructions, or generic computer/computer components to carry out the exception. The recitation of generic computer instruction and computer components to apply the judicial exception do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101. Regarding claim 2, 5, 9, 11, 16, 19, 22, 24, 29 the limitation of interval description, power buffer, what a HW entity is, cycles bit used, memory power, details of a mesh, details of the device, are considered mere instructions, or generic computer/computer components to carry out the exception Accordingly, the additional element recited in claim 3 fails to provide a practical application under prong 2, or amount to significantly more under step 2B. Regarding claim 3, 6, 26 the limitations determining and accumulate a sum are functions that can be reasonably performed in the human mind, thus, additional mental process defined in the claims. The claim does not include any additional element, thus, no limitation that needs to be analyzed under prong 2 for practical application, or under step 2B for significantly more. Regarding claim 4, 7, 30 the limitation of an identifier, association of the entities, the power buffer, and identifiers of a VM are considered mere instructions, or generic computer/computer components to carry out the exception Accordingly, the additional element fails to provide a practical application under prong 2, or amount to significantly more under step 2B. The limitations of recording are nothing more than insignificant extra solution activity which is not a practical application under prong 2. Under step 2B, the courts of identified the generic function of gathering/storing data, the results of the judicial exception, is well-understood, routine and conventional activity. Regarding claim 7, 8, 10, 12, 14, 15, 17, 18, 20, 21, 27, 28 the limitation association of the entities, what entities include, what power represents, entities include cores, memory controllers, ports are considered mere instructions, or generic computer/computer components to carry out the exception Accordingly, the additional element fails to provide a practical application under prong 2, or amount to significantly more under step 2B. The limitations of determining, accumulating, assigning are functions that can be reasonably performed in the human mind, thus, additional mental process defined in the claims. Regarding claim 13, 23, the limitations of recording values, reporting information, are nothing more than insignificant extra solution activity which is not a practical application under prong 2. Under step 2B, the courts of identified the generic function of gathering/storing data, the results of the judicial exception, is well-understood, routine and conventional activity. See MPEP 2106.05(d) - i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)”. Claim Interpretation - 35 USC § 112 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-34-21 Claim limitation 1 has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “microcontroller” coupled with functional language without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier. Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim 13 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof. A review of the specification, Fig. 1 [0100] shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation. If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action. If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011). Claim Rejections - 35 USC §103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim /s 1, 3, 4, 5, 6, 25, 26, 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacNamara (Pub. No. US 2022/0011843) in view of Siddiqui (Pub. No. US 2023/0409368) . Claim 1, 25 MacNamara teaches “A compute node, comprising: a plurality of hardware (HW) entities associated with executions of one or more virtual machines (VM) ([Fig. 1, 116] VM with platform resources [0018] The platform resources 116 comprise one or more integrated circuit components. Individual integrated circuit components comprise one or more processor units and may also comprise non-processor unit circuitry, as described above. The platform resources 116 can further comprise platform-level components such as voltage regulators and a baseboard management controller (BMC). In one embodiment, the computing device 104 is a server, and the platform resources 116 comprise one or more multi-core server processors.), …, one or more first HW entities of the plurality of HW entities being associated with an execution of a first VM of the one or more VMs during a digital power meter (DPM) interval, …; and a microcontroller (Mpro) configured to: determine, for the first VM, a first VM power representing power consumed by the one or more first HW entities while executing the first VM during the DPM interval ([0037] The telemetry information 164 can be provided in various measures or formats, depending on the telemetry information being provided. For example, time-related telemetry information can be provided in an amount of time (e.g., ns) or a percentage of a monitoring period (the time between the provision of successive instances of telemetry information by a computing device component to the telemetry agent 168). For telemetry information relating to a list of cores, cores can be identified by a core identifier. Telemetry information relating to utilization (e.g., physical processor unit utilization, virtual processor unit utilization, memory controller utilization, memory utilization, interconnector controller utilization) (i.e. hardware entities) can be provided as, for example, a number of cycle counts, an amount of power consumed in watts, an amount of bandwidth consumed in gigabytes/second, or a percentage of a full utilization of the resource by a software entity. Telemetry information for processor units can be for logical or physical processor units. Telemetry information relating to frequency can be provided as an absolute frequency in hertz, or a percentage of a reference or characteristic frequency of a component (e.g., base frequency, maximum turbo frequency). Telemetry information related to power consumption can be provided as an absolute power number in watts or a relative power measure (e.g., current power consumption relative to a characteristic power level, such as TDP (thermal design profile). [0008] The technologies described herein provide for the estimation and monitoring of power consumed by individual software entities, such as virtual machines, containers, network slices, and other applications executing on a computing device. [0085] FIG. 3 is a flowchart of an example software entity power consumption estimation method. The method 300 can be performed by, for example, a power estimator that is part of a management and orchestration system for a data center. At 310, telemetry information associated with a computing platform on which a software entity is executing is received, the computing platform comprising an integrated circuit component comprising a plurality of physical processor units and non-processor unit circuitry, the software entity executing on a virtual processor unit to which one or more of the physical processor units are allocated. At 320, a software entity power consumption for the software entity is determined based on the telemetry information.)”. However, MacNamara may not explicitly teach details of the VM provided by the hypervisor. Siddiqui teaches as evidence, a hypervisor instantiates VM such that teaches “each VM being an instantiation of a software (SW) entity of one or more SW entities… the first VM being an instantiation of a first SW entity for execution on the compute node ([0029] The hypervisor 210 enables multiple virtual machine nodes 208 to be implemented on computing device 200 by allocating portions of the physical resources 204, 206 of the computing devices 200, such as processing time, memory, and disk storage space, to each virtual machine node 208. Hypervisor 210 may be configured to implement any suitable number of virtual machine nodes 208 on the computing device 200. The hypervisor 210 of FIG. 2 is shown has having instantiated three virtual machine nodes 208. Computing device 200 may be capable of supporting more virtual machine nodes as indicated by placeholder nodes 216. Hypervisor may be configured to instantiate any suitable number of virtual machine nodes 208 on computing device 200 depending on various factors, such as hardware configuration, software configuration, application, and the like.)”. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Siddiqui with the teachings of MacNamara in order to provide a system that teaches VM instantiation. The motivation for applying Siddiqui teaching with MacNamara teaching is to provide evidence MacNamara’s hypervisor instantiated the VMs for the purposes of design choice. MacNamara and Siddiqui are analogous art directed towards virtual environments. Together MacNamara and Siddiqui teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Siddiqui with the teachings of MacNamara by known methods and gained expected results. Claim 3, 26 the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 1, wherein in determining the first VM power, the Mpro is configured to: determine, for each first HW entity associated with the execution of the first VM during the DPM interval, a first HW entity power representing power consumed by that first HW entity while the first VM is being executed, and accumulate the first HW entity powers across the one or more HW entities, the first VM power comprising the accumulated sum of the first HW entity powers ([0122] Example 2 comprises the method of example 1, wherein the telemetry information comprises information indicating an integrated circuit component power consumption and determining the software entity power consumption comprises: determining a per-processor unit power consumption based on the integrated circuit component power consumption and a number of physical processor units in the plurality of physical processor units; and determining the software entity power consumption by scaling the per-processor unit power consumption by a sum of a processor unit power consumption scaling factor indicating a portion of integrated circuit component power consumed by the plurality of the physical processor units and a non-processor unit circuitry power consumption scaling factor indicating a portion of integrated circuit component power consumed by the non-processor unit circuitry.)”. Claim 4, 30 the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 3, further comprising: a power buffer, wherein the one or more VMs are each identified with a VM identifier (VMID), a first VMID identifying the first VM, and wherein the Mpro is further configured to record the first VM power in the power buffer as being associated with the first VMID ([0072] In some embodiments, a software entity can be associated with a user entity via a user identifier. The user identifier can be a number, alphanumeric string, or other information suitable for identifying a user entity. In some embodiments, the user identifier associated with a software entity can be provided to the computing device 104 when the software entity is sent to the computing device 104 for execution. The telemetry information 164 can comprise the user identifier for a software entity if the telemetry information 164 comprises metrics pertaining to a software entity, such as the utilization of a virtual processor unit, memory controller, or interconnect controller by a software entity. The power estimator 172 can store the user identifier, and software entity power consumption for a software entity in the database 174 after determining the software entity power consumption for a software entity. The power estimator 172 can provide the user identifier for a software entity to the controller 112 when providing the software entity power consumption for the software entity to the controller. Similarly, a network slice identifier can be used to associate multiple software entities comprising a network slice to allow for the reporting of total power consumption by a network slice operating on a computing device (or across multiple computing devices) and to allow for a user entity to be billed based on the total power consumption by a network slice.)”. Claim 5, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 4, wherein the power buffer is separate from memories and/or buffers used to hold data in execution of the one or more VMs ([0066] The software entity power consumptions determined by the power estimator 172 can be displayed on a display 180 that is local to any component of the system 100 (e.g., controller 112, computing device 104, monitoring and analytics system 108) or remote to the system 100. Further, software entity power consumptions can be stored at a database 184. The database 184 can be local or remote to any component of the system 100. The database 184 can be a centralized database stored at one computing device or distributed database stored across multiple computing devices. The database 184 can be updated with current software entity power consumption on a periodic or any other basis. The database 184 can be updated by any component of the system 100 (e.g., controller 112, computing device 104, power estimator 172).)”. Claim 6, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 3, wherein the Mpro is configured to determine multiple first VM powers corresponding to multiple DPM intervals when the first VM is executed over the multiple DPM intervals ([0078] The power estimator 172 can determine software entity power consumption information at any periodic or another interval. For example, the power estimator can determine software entity power consumption information at intervals of N seconds, minutes, hours, days, etc. The power estimator 172 can provide the software entity power consumption to the controller 112 at any periodic or another interval, and the interval at which the power estimator 172 provides information to the controller 112 can be different or the same as the interval at which it determines the software entity power consumptions. The controller 112 can determine whether an action is to be taken based on the software entity power consumption information received over any periodic or another time interval. [0034] The software entity power consumption of an application that is part of a network slice can be summed with the software entity power consumption of one or more other applications that are part of a network slice to determine a power consumption for the network slice. In embodiments where the application 136 or 140 a UPF, the application telemetry can comprise UPF KPIs. In the application is not instrumented to generate application telemetry information, in some embodiments, the controller 112 can instrument the application to provide application telemetry.)” . 07-21-aia AIA Claim /s 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacNamara, Siddiqui in further view of Fugitt (Pub. No. US 2016/0156502) . Claim 2, the combination may not explicitly teach a periodic less than a second. Fugitt teaches “the compute node of claim 1, wherein the DPM interval is 500 µs or less ([0044] In some embodiments, the master broker sends a heartbeat signal to the master election module 230 at periodic intervals, for example, a heartbeat is sent every microsecond.)”. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Fugitt with the teachings of MacNamara, Siddiqui in order to provide a system that teaches details periodic intervals. The motivation for applying Fugitt teaching with MacNamara, Siddiqui teaching is to provide evidence MacNamara’s monitoring can be less than a second for the purposes of design choice. MacNamara, Siddiqui, Fugitt are analogous art directed towards virtual environments. Together MacNamara, Siddiqui, Fugitt teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Fugitt with the teachings of MacNamara, Siddiqui by known methods and gained expected results . 07-21-aia AIA Claim /s 7- 15, 20, 21, 23, 24, 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacNamara, Siddiqui in further view of Hunt (Pub. No. US 2022/0368771) . Claim 7, 12, 27 the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 1, wherein one or more second HW entities of the plurality of HW entities are associated with an execution of a second VM of the one or more VMs during the DPM interval, the second VM being an instantiation of a second SW entity for execution on the compute node, … and wherein the Mpro is configured to determine, for the second VM, a second VM power representing power consumed by the one or more second HW entities while the second VM is being executed during the DPM interval ([0177] Example 57 comprises the computing system of any one of examples 36-56, wherein the software entity is a first software entity and the software entity power consumption of the first software entity is a first software entity power consumption, the first software entity and one or more second software entities are associated with a user entity, individual of the second software entities having an associated second software entity power consumption, the instructions stored on the one or more computer-readable media further cause the one or more first physical processor units to: sum the first software entity power consumption and the second software entity power consumptions to generate a total software entity power consumption; determine that the total software entity power consumption exceeds a power budget; and cause an action to be taken to reduce the first software entity power consumption.)”. However, the combination may not explicitly teach further details of the hypervisor. Hunt teaches “the first and second SW entities being different from each other ([Claim 2] A non-transitory processor-readable medium storing code representing instructions configured to be executed by a control cluster module to cause the control cluster module to: instantiate a first virtual machine in a first commercial cloud; instantiate a second virtual machine in a second commercial cloud; instantiate a third virtual machine in a third commercial cloud, the third hypervisor being different from the first hypervisor, the third commercial cloud being different from the first commercial cloud; instantiate a fourth virtual machine in a fourth commercial cloud, the fourth hypervisor being different from the second hypervisor,)”. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Hunt with the teachings of MacNamara, Siddiqui in order to provide a system that teaches details of hypervisors. The motivation for applying Hunt teaching with MacNamara, Siddiqui teaching is to provide evidence MacNamara’s VMs may be instantiated from different hypervisors for the purposes of design choice. MacNamara, Siddiqui, Hunt are analogous art directed towards virtual environments. Together MacNamara, Siddiqui, Hunt teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Hunt with the teachings of MacNamara, Siddiqui by known methods and gained expected results. Claim 8, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 7, wherein at least one core is configured to execute at least a portion of the first VM and at least a portion of the second VM during the DPM interval, and wherein the Mpro is configured to determine first and second core powers, the first core power representing power consumed by the at least one core in executing the first VM during the DPM interval, the first core power being included in the first VM power, and the second core power representing power consumed by the at least one core in executing the second VM during the DPM interval, the second core power being included in the second VM power ([0177] Example 57 comprises the computing system of any one of examples 36-56, wherein the software entity is a first software entity and the software entity power consumption of the first software entity is a first software entity power consumption, the first software entity and one or more second software entities are associated with a user entity, individual of the second software entities having an associated second software entity power consumption, the instructions stored on the one or more computer-readable media further cause the one or more first physical processor units to: sum the first software entity power consumption and the second software entity power consumptions to generate a total software entity power consumption; determine that the total software entity power consumption exceeds a power budget; and cause an action to be taken to reduce the first software entity power consumption. [0037] The telemetry information 164 can be provided in various measures or formats, depending on the telemetry information being provided. For example, time-related telemetry information can be provided in an amount of time (e.g., ns) or a percentage of a monitoring period (the time between the provision of successive instances of telemetry information by a computing device component to the telemetry agent 168). For telemetry information relating to a list of cores, cores can be identified by a core identifier. Telemetry information relating to utilization (e.g., physical processor unit utilization, virtual processor unit utilization, memory controller utilization, memory utilization, interconnector controller utilization) can be provided as, for example, a number of cycle counts, an amount of power consumed in watts, an amount of bandwidth consumed in gigabytes/second, or a percentage of a full utilization of the resource by a software entity. Telemetry information for processor units can be for logical or physical processor units.). Claim 9, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 7, wherein at least one first HW entity is different from at least one second HW entity ([0037] The telemetry information 164 can be provided in various measures or formats, depending on the telemetry information being provided. For example, time-related telemetry information can be provided in an amount of time (e.g., ns) or a percentage of a monitoring period (the time between the provision of successive instances of telemetry information by a computing device component to the telemetry agent 168). For telemetry information relating to a list of cores, cores can be identified by a core identifier. Telemetry information relating to utilization (e.g., physical processor unit utilization, virtual processor unit utilization, memory controller utilization, memory utilization, interconnector controller utilization) (i.e. hardware entitites) can be provided as, for example, a number of cycle counts, an amount of power consumed in watts, an amount of bandwidth consumed in gigabytes/second, or a percentage of a full utilization of the resource by a software entity. Telemetry information for processor units can be for logical or physical processor units.)” . Claim 10, 28 the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 7, wherein the plurality of HW entities includes a plurality of cores configured to execute the one or more VMs, one or more first cores of the plurality of cores executing the first VM during the DPM interval, and wherein in determining the first VM power, the Mpro is configured to: determine, for each first core, a first core power representing power consumed by that first core while executing the first VM during the DPM interval, and accumulate the first core powers across the one or more first cores, the first VM power comprising the accumulated sum of the first core powers ([0122] Example 2 comprises the method of example 1, wherein the telemetry information comprises information indicating an integrated circuit component power consumption and determining the software entity power consumption comprises: determining a per-processor unit power consumption based on the integrated circuit component power consumption and a number of physical processor units in the plurality of physical processor units; and determining the software entity power consumption by scaling the per-processor unit power consumption by a sum of a processor unit power consumption scaling factor indicating a portion of integrated circuit component power consumed by the plurality of the physical processor units and a non- processor unit circuitry power consumption scaling factor indicating a portion of integrated circuit component power consumed by the non-processor unit circuitry.)” . Claim 11, 29 the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 10, wherein cycles of the plurality of cores are not used in determining the first VM power ([0037] The telemetry information 164 can be provided in various measures or formats, depending on the telemetry information being provided. For example, time-related telemetry information can be provided in an amount of time (e.g., ns) or a percentage of a monitoring period (the time between the provision of successive instances of telemetry information by a computing device component to the telemetry agent 168). For telemetry information relating to a list of cores, cores can be identified by a core identifier. Telemetry information relating to utilization (e.g., physical processor unit utilization, virtual processor unit utilization, memory controller utilization, memory utilization, interconnector controller utilization) can be provided as, for example, a number of cycle counts, an amount of power consumed in watts, an amount of bandwidth consumed in gigabytes/second, or a percentage of a full utilization of the resource by a software entity.)”. Claim 13, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 12, wherein the Mpro is configured to record in a power buffer, for each DPM interval of multiple DPM intervals, the first and second VM powers corresponding to that DPM interval ([0177] Example 57 comprises the computing system of any one of examples 36-56, wherein the software entity is a first software entity and the software entity power consumption of the first software entity is a first software entity power consumption, the first software entity and one or more second software entities are associated with a user entity, individual of the second software entities having an associated second software entity power consumption, the instructions stored on the one or more computer-readable media further cause the one or more first physical processor units to: sum the first software entity power consumption and the second software entity power consumptions to generate a total software entity power consumption; determine that the total software entity power consumption exceeds a power budget; and cause an action to be taken to reduce the first software entity power consumption. [0066] database)” . Claim 14, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 10, wherein the plurality of HW entities includes one or more memory controllers, and wherein the Mpro is configured to: determine, for each memory controller, a first memory power representing power used to access memory associated with the first VM as instructed by that memory controller during the DPM interval, and accumulate the first memory powers across the one or more memory controllers, the first VM power comprising the accumulated sum of the first memory powers ([0027] Platform telemetry information can further comprise one or more of the following: information indicating one or more operating frequencies of the non-processor unit circuitry of the integrated circuit component, information indicating an operating frequency of a memory controller of the integrated circuit component, information indicating a utilization of a memory external to the integrated circuit component by a software entity, information indicating a total memory controller utilization by software entities executing on the integrated circuit component, information indicating an operating frequency of individual interconnect controllers of an integrated circuit component, information indicating a utilization of an interconnect controller by a software entity, and information indicating a total interconnect controller utilization by the software entities executing on an integrated circuit component.)”. Claim 15, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 10, wherein the plurality of HW entities includes one or more memory controllers, and wherein the Mpro is configured to: determine total memory power representing power used to access memory associated with all VMs active during the DPM interval including the first and second VMs, assign a first memory power to the first VM, the first memory power representing a first portion of the total memory power, the first VM power comprising the first memory power, and assign a second memory power to the second VM, the second memory power representing a second portion of the total memory power, the second VM power comprising the second memory power ([0056] Equation 5 is similar to equation 1 but with the non-processor unit circuitry scaling factor SF.sub.npu scaled by a memory utilization scaling factor SF.sub.mem_util. The SF.sub.mem_util can be based on the following telemetry information 164: a utilization by the software entity of memory external to the integrated circuit component (and controlled by a memory controller that is part of the non-processor unit circuitry) and the utilization of the memory by one or more additional software entities executing on the same integrated circuit component as the software entity. In some embodiments, the memory scaling factor SF.sub.mem_util is a ratio of the utilization by the software entity of the memory to an average utilization of the memory by one or more software entities executing on the integrated circuit component. If the software entity is utilizing more of the memory relative to an average utilization of the memory by one or more software entities executing on the integrated circuit component, SF.sub.mem_util is greater than 1.0. If the software entity is utilizing less of the memory relative to an average utilization of memory by one or more software entities executing on the integrated circuit component, SF.sub.mem_util is less than 1.0.)”. Claim 20, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 10, wherein the plurality of HW entities includes one or more meshes, and wherein the Mpro is configured to: determine, for each mesh, a first mesh power representing power used by that mesh associated with the first VM during the DPM interval, and accumulate the first mesh powers across the one or more meshes, the first VM power comprising the accumulated sum of the one or more first mesh powers ([0070] If the software entity consumption information is for an application that is part of a network slice, the controller 112 can sum the software entity power consumptions for applications that comprise a network slice and report a total software entity power consumption for a network slice operating on a computing system (or across multiple computing systems). As used herein, the term “network slice” refers to a logical or virtualized network operating on a physical network structure and can comprise applications responsible for network slice implementation (e.g., application that comprise the service or network function layer of the network slice) or network slice control or orchestration. Reports can be generated at periodic intervals (e.g., N seconds, minutes, hours, or days), other intervals, or in response to a request for a power consumption report. [0072] Similarly, a network slice identifier can be used to associate multiple software entities comprising a network slice to allow for the reporting of total power consumption by a network slice operating on a computing device (or across multiple computing devices) and to allow for a user entity to be billed based on the total power consumption by a network slice.)”. Claim 21, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 10, wherein the plurality of HW entities includes one or more meshes, and wherein the Mpro is configured to: determine total mesh power representing power used by the one or more meshes during the DPM interval, assign a first mesh power to the first VM, the first mesh power representing a first portion of the total mesh power, the first VM power comprising the first mesh power, and assign a second mesh power to the second VM, the second mesh power representing a second portion of the total mesh power, the second VM power comprising the second mesh power ([0070] If the software entity consumption information is for an application that is part of a network slice, the controller 112 can sum the software entity power consumptions for applications that comprise a network slice and report a total software entity power consumption for a network slice operating on a computing system (or across multiple computing systems). As used herein, the term “network slice” refers to a logical or virtualized network operating on a physical network structure and can comprise applications responsible for network slice implementation (e.g., application that comprise the service or network function layer of the network slice) or network slice control or orchestration. Reports can be generated at periodic intervals (e.g., N seconds, minutes, hours, or days), other intervals, or in response to a request for a power consumption report. [0072] Similarly, a network slice identifier can be used to associate multiple software entities comprising a network slice to allow for the reporting of total power consumption by a network slice operating on a computing device (or across multiple computing devices) and to allow for a user entity to be billed based on the total power consumption by a network slice.)”. Claim 23, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 7, wherein the Mpro is configured to report the first and second VM powers to an operating system (OS) ([0083] FIG. 2 illustrates a block diagram of an example computing system in which the power estimator is implemented as part of a 3GPP Network Data Analytics Function (NWDAF). The computing system 200 comprises a computing device 204 on which an application 236 is operating on virtual machine 228. The virtual machine 228 is operating on a hypervisor 224 that is in turn operating on an operating system 220. The operating system 220 is executing on the platform resources 216 (e.g., integrated circuit components) of the computing device 204. The application 236 is an element of a 3GPP 5G core infrastructure and part of a network slice. An NWDAF application agent 238 provides application telemetry 266, such as information indicating the utilization of the virtual processor unit on which the application 236 is executing to a power estimator 272 that is part of an NWDAF 284. Platform telemetry information 262 and virtualization telemetry information 264 are provided by the platform resources 216, the operating system 220, and the hypervisor 224 to a telemetry agent 268.)”. Claim 24, the combination teaches the claim, wherein MacNamara teaches “the compute node of claim 1, wherein the compute node is a system-on-chip (SoC) device ([0105] It is to be understood that FIG. 4 illustrates only one example computing system architecture. Computing systems based on alternative architectures can be used to implement technologies described herein. For example, instead of the processors 402 and 404 and the graphics engine 452 being located on discrete integrated circuits, a computing system can comprise an SoC (system-on-a-chip) integrated circuit incorporating multiple processors, a graphics engine, and additional components. Further, a computing system can connect its constituent component via bus or point-to-point configurations different from that shown in FIG. 4. Moreover, the illustrated components in FIG. 4 are not required or all-inclusive, as shown components can be removed and other components added in alternative embodiments.)” . 07-21-aia AIA Claim /s 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacNamara, Siddiqui, Hunt in further view of Ramirez (Pub. No. US 2014/0019823) . Claim 16, the combination may not explicitly teach a periodic less than a second. Ramirez teaches “the compute node of claim 15, wherein the first memory power is equal to the second memory power, or wherein the first memory power is proportional to first core power and the second memory power is proportional to the second core power ([Claim 8] The apparatus of claim 1, wherein the first cache portion has a first supply voltage, the second cache portion has a second supply voltage, and the third cache portion has a third supply voltage, and wherein the first supply voltage is less than or equal to the second supply voltage, and the second supply voltage is less than or equal to the third supply voltage.)”. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Ramirez with the teachings of MacNamara, Siddiqui, Hunt in order to provide a system that teaches details memory power. The motivation for applying Ramirez teaching with MacNamara, Siddiqui, Hunt teaching is for the purposes of design choice. MacNamara, Siddiqui, Hunt, Ramirez are analogous art directed towards distributed environments. Together MacNamara, Siddiqui, Hunt, Ramirez teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Ramirez with the teachings of MacNamara, Siddiqui, Hunt by known methods and gained expected results . 07-21-aia AIA Claim /s 17-19, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacNamara, Siddiqui, Hunt in further view of Lin (Pub. No. US 2016/0231959) . Claim 17, the combination may not explicitly teach the limitation. Lin teaches “the compute node of claim 10, wherein the plurality of HW entities includes one or more input/output (I/O) ports, and wherein the Mpro is configured to: determine, for each I/O port, a first I/O power representing power used by that I/O port associated with the first VM during the DPM interval, and accumulate the first I/O powers across the one or more I/O ports, the first VM power comprising the accumulated sum of the first I/O powers ([0061] It should be noted that, for the first storage area 111, if, by controlling the input voltages of the first port 11, the second port 12, the first drive port 40, and the second drive port 50, a voltage difference between two ends (that is, the first port 11 and the second drive port 50) of the first storage area 111 is greater than or equal to a voltage threshold for driving a magnetic domain to move and a voltage difference between two ends (that is, the second port 12 and the first drive port 40) of the second storage area 112 is less than the voltage threshold for driving a magnetic domain to move, and in addition, a value of a voltage of the first gate port 201 is controlled to connect the first drive circuit 20 and a value of a voltage of the second gate port 301 is controlled to disconnect the second drive circuit 30, then under driving of the first drive circuit 20, a current pulse is generated in the first storage area 111, and a magnetic domain in the first storage area 111 is driven to move, thereby completing a read operation or a write operation on the first storage area 111. In addition, it is easily figured out that a voltage at two ends of a storage area in the storage unit 100 is proportional to a moving distance of a magnetic domain, that is, when a moving distance becomes longer, to maintain a same moving speed of a magnetic domain, it is required to increase the voltage at the two ends of the corresponding storage area.)”. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Lin with the teachings of MacNamara, Siddiqui, Hunt in order to provide a system that teaches details memory resources of MacNamara are ports. The motivation for applying Lin teaching with MacNamara, Siddiqui, Hunt teaching is for the purposes of design choice. MacNamara, Siddiqui, Hunt, Lin are analogous art directed towards distributed environments. Together MacNamara, Siddiqui, Hunt, Lin teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Lin with the teachings of MacNamara, Siddiqui, Hunt by known methods and gained expected results. Claim 18, the combination may not explicitly teach the limitation. Lin teaches “the compute node of claim 10, wherein the plurality of HW entities includes one or more input/output (I/O) ports, and wherein the Mpro is configured to: determine a total I/O power representing power used by the one or more IO ports during the DPM interval, assign a first I/O power to the first VM, the first I/O power representing a first portion of the total I/O power, the first VM power comprising the first I/O power, and assign a second I/O power to the second VM, the second I/O power representing a second portion of the I/O power, the second VM power comprising the second I/O power ([0061] It should be noted that, for the first storage area 111, if, by controlling the input voltages of the first port 11, the second port 12, the first drive port 40, and the second drive port 50, a voltage difference between two ends (that is, the first port 11 and the second drive port 50) of the first storage area 111 is greater than or equal to a voltage threshold for driving a magnetic domain to move and a voltage difference between two ends (that is, the second port 12 and the first drive port 40) of the second storage area 112 is less than the voltage threshold for driving a magnetic domain to move, and in addition, a value of a voltage of the first gate port 201 is controlled to connect the first drive circuit 20 and a value of a voltage of the second gate port 301 is controlled to disconnect the second drive circuit 30, then under driving of the first drive circuit 20, a current pulse is generated in the first storage area 111, and a magnetic domain in the first storage area 111 is driven to move, thereby completing a read operation or a write operation on the first storage area 111. In addition, it is easily figured out that a voltage at two ends of a storage area in the storage unit 100 is proportional to a moving distance of a magnetic domain, that is, when a moving distance becomes longer, to maintain a same moving speed of a magnetic domain, it is required to increase the voltage at the two ends of the corresponding storage area.)”. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Lin w