DETAILED ACTION
Claims 1 – 20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 – 12 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 and 19 describe that “the determining that the at least one register of the two or more registers comprises the all-zeros value is based at least in part on a mnemonic associated with the store instruction”, and claim 12 describes that “the mnemonic comprises a zero register (XZR) mnemonic”. It appears that this presents a discrepancy, as claim 11 has the mnemonic associated with the instruction, while claim 12 has the mnemonic describing a register. The specification seems to describe in paragraph [0026] that the presence of the mnemonic describing the zero register is present within the instruction, and based on the mnemonic describing the zero register being present within the instruction that the store zero micro-operation may be triggered. If this is the case, then the examiner recommends making it clear that the mnemonic is not “associated” with the store instruction, but rather describes an all zero register and if that mnemonic is found within a store instruction, then the store all zero micro-operation will be generated. Claim 12 is rejected for at least its dependence upon rejected claim 11 and because it does not cure the deficiencies found within claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1 – 7, 13-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Carro et al (US 2018/0307491, hereinafter referred to as Carro).
As per claims 1, 13 and 20:
Taking claim 1 as exemplary: Carro discloses a method for instruction decoding, comprising obtaining a store instruction that involves two or more registers (Carro: Paragraphs [0056] and [0059]); determining that at least one register of the two or more registers comprises an all-zeros value (Carro: Paragraph [0056], the predicate register having a value of zero); and decoding the store instruction to include a store-zeros micro-operation based at least in part on the determining (Carro: Paragraph [0056], if predicate register p0 contains a zero value, the destination register will be set to zero value).
As per claims 2 and 14:
Taking claim 2 as exemplary: Carro discloses a first number of registers used by the store- zeros micro-operation is fewer than a second number of the two or more registers of the store instruction (Carro: Paragraph [0056], using registers p0 and x1).
As per claim 3:
Carro discloses the first number is two and the second number is three (Carro: Paragraph [0056]).
As per claims 4 and 15:
Taking claim 4 as exemplary: Carro discloses a first register of the two or more registers is encoded in a first instruction field of the store instruction and comprises a first value to be stored in a cache memory, a second register of the two or more registers is encoded in a second instruction field of the store instruction and comprises a second value to be stored in the cache memory, and a third register of the two or more registers is encoded in a third instruction field of the store instruction and comprises a base register value (Carro: Paragraph [0056] – [0058], interpreting register p0 as equivalent to the claimed first register, register z1 as equivalent to the claimed second register, and register x1 as equivalent to the claimed third register as x1 contains a bass address).
As per claim 5:
Carro discloses the store-zeros micro-operation uses the third register as a first source register and the first register as a second source register for executing the store-zeros micro-operation (Carro: Paragraph [0056] registers x1 and p0).
As per claim 6:
Carro discloses the store instruction comprises a store pair of registers (STP) instruction, and the store-zeros micro-operation is a single memory-based micro-operation decoded for the STP instruction (Carro: Paragraphs [0049] and [0056], the instruction is broken into two micro-operations, interpreting this as performing the functionality of the claimed store pair of registers instruction).
As per claim 7:
Carro discloses scheduling the store-zeros micro-operation for execution; calculating a memory address based at least in part on the base register value; and storing, based at least in part on executing the store-zeros micro-operation, an all-zeros value in the cache memory corresponding to the calculated memory address (Carro: Paragraph [0056], interpreting cache memory as including destination register z2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 – 10 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Carro as applied to claims 1 and 13 above, and further in view of Ray et al (US 2021/0035258, hereinafter referred to as Ray).
As per claims 8 and 16:
Taking claim 8 as exemplary: Carro discloses scheduling the store-zeros micro-operation for execution; and storing, based at least in part on executing the store-zeros micro-operation, an all-zeros value in a store queue register of a cache memory (Carro: Paragraph [0056]).
Carro does not specifically describe setting zeros-indicating metadata to indicate that the store queue register includes the all-zeros value.
However, Ray teaches setting zeros-indicating metadata to indicate that the register includes the all-zeros value (Ray: Paragraph [0397]) in order to use the metadata to assist with compression of the destination data stored in the cache and memory (Ray: Paragraph [0398]). It would have been obvious to one or ordinary skill in the art at the time of filing for Carro to implement the setting zeros-indicating metadata to indicate that the register includes the all-zeros value as taught by Ray in order to use the metadata to assist with compression of the destination data stored in the cache and memory (Ray: Paragraph [0398]).
As per claims 9 and 17:
Carro does not specifically disclose refraining from accessing the store queue register for a micro-operation executed subsequent to the store-zeros micro-operation based at least in part on the zeros-indicating metadata.
However, Ray teaches the use of the metadata is to assist with the compression of the destination data, and as such it would have been obvious to one of ordinary skill in the art at the time of filing for Carro to not access the register for subsequent operations if the result data stored with the metadata is to be compressed.
As per claims 10 and 18:
The modified Carro discloses that the zeros-indicating metadata comprises one or more indicator bits, and a number of the one or more indicator bits is fewer than a number of bits in a cache line of a data element corresponding to the store queue register (Carro: Paragraph [0397], the zero detection meta data may be a bitfield that includes one bit per vector element).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Anderson et al (US 2022/0244880) teaches the use of clearing registers to an all zero value with the use of a single instruction. Bshara et al (US 10,901,492) teaches the use of meta data to indicate attributes of data stored in architectural registers, such as if the data is zero or not.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZACHARY K HUSON whose telephone number is (571)270-3430. The examiner can normally be reached Monday - Friday 7:00 - 3:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZACHARY K HUSON/Primary Examiner, Art Unit 2181