DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed on 12/17/2025. Claims 1-24 are pending in the Application, of which Claims 1, 9 and 17 are independent.
Continuity/Priority information
The present Application 18490762 filed 10/20/2023 claims foreign priority to TAIWAN, Application No. 112131966, filed 08/24/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 12/17/2025with respect to the rejection of Claims 1-24 under 35 U.S.C. 102(a)(1) as being anticipated by Uchikawa et al. (Pub. No. US 20110219284), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of KANEKO (Pub. No. US 20230075492) Pub. Date: 2023-03-09, as set forth in the present office action.
Applicant argues that Uchikawa fails to teach the feature “wherein the first error evaluation information comprises an evaluation value which is obtained based on a logical operation performed on multiple data frames read respectively from multiple physical units in the physical unit group; and performing a second single-frame decoding on the first data frame according to the first error evaluation information” as recited in independent claim 1.
In response to Applicant arguments, the above feature is disclosed by KANEKO, as described in more detailed in the office action below, see Para. [0044] - [0046] FIGS. 4 and 5.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANEKO (Pub. No. US 20230075492) Pub. Date: 2023-03-09.
Regarding independent Claims 1, 9 and 17, KANEKO discloses a memory system and method including a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips, comprising:
transmitting a read command sequence, ….to read a first physical unit, wherein the first physical unit belongs to a physical unit group;
[0031] As illustrated in FIG. 1, the memory system 1 includes a controller 11 and non-volatile memory chips 12 “physical units”. [0032] The controller 11 is a device that controls writing of data into the non-volatile memory chip 12 or reading of data from the non-volatile memory chip 12 in response to a command “read command” from the host 2. The controller 11 is configured as, for example, a system-on-a-chip (SoC).
performing a first single-frame decoding on a first data frame read from the first physical unit; [0034] FIG. 1, The controller 11 includes an error correction circuit 100. A data error may occurs in the non-volatile memory chip 12. The error correction circuit 100 is, for example, a device that detects and corrects an error in read data when the corresponding data is read from the non-volatile memory chip 12. In the memory system 1 according to the first embodiment, regarding a data frame that is written into a plurality of non-volatile memory chips 12 in a distributed manner, data error correction capable of coping with chip failure is implemented by the error correction circuit 100 “single-frame decoding”.
wherein the first error evaluation information comprises an evaluation value which is obtained based on a logical operation performed on multiple data frames read respectively from multiple physical units in the physical unit group;
[0044] FIGS. 4 and 5, For example, when a read command is received from a host, the controller executes reading of data from non-volatile memory chips on the basis of a logical address specified by the read command. Here, exemplified is a case where a data frame including data corresponding to an address X (addr X) is read from 10 non-volatile memory chips.
[0045] Therefore, even when there is a bit error in a data frame (or an input data frame) read from the 10 non-volatile memory chips, when the number of error bits of the entire data frame is equal to or less than the error correction ability T of the ECC decoder (i.e., when the number of error bits ≤T), a data frame (or an output data frame) in which the corresponding error bits are corrected and no bit error is present may be obtained corresponding to “evaluation value”.
[0046] FIG. 4, FIG. 5 illustrates a case where a data frame including data corresponding to an address X (addr X) is read from 10 non-volatile memory chips “multiple physical units”, in which a chip failure occurs in one of the 10 corresponding non-volatile memory chips. The failed chip is a non-volatile memory chip connected to a channel #6.
performing a second single-frame decoding on the first data frame according to the first error evaluation information. [0047] When a chip failure occurs, a portion of the data frame corresponding to the failed chip is entirely lost. Thus, the corresponding portion becomes error bits, and the error bits of the entire data frame largely exceed the error correction ability T of the ECC decoder. Therefore, correction using an error correction bit is no longer possible.
Regarding Claims 2, 10, 18, KANEKO discloses updating the first error evaluation information according to a decoding result of the third single-frame decoding in response to the third single-frame decoding being successful; [0057] When the ECC decoding of the “Frame #0” is failed (S104: No), the error correction circuit 100 first sets data of the channel 1 as a restoration target (S105), and generates a data frame “Frame #N” in which data of a channel N (initially 1) as the restoration target is restored by bit XOR of the other channels (S106). The error correction circuit 100 performs ECC decoding on the corresponding generated “Frame #N” (S107).
Regarding Claims 3, 4, 11, 12, 19, 20, KANEKO discloses wherein the first physical unit belongs to a target physical unit, and the second physical unit belongs to a non- target physical unit for assisting in decoding of the first data frame, and obtaining second error evaluation information corresponding to at least one candidate physical unit in the physical unit group, wherein the at least one candidate physical unit does not include the first physical unit; and determining the second physical unit from the at least one candidate physical unit according to the second error evaluation information. [0043] FIG. 4 illustrates a state where a data frame including user data and an error correction bit (ECC Parity) is written into 10 non-volatile memory chips connected to 10 channels #1 to #10, respectively, in a distributed manner. The channels #1 to #10 include communication lines (memory bus) by which a controller communicates with the non-volatile memory chips. To each of the channels #1 to #10, one or more non-volatile memory chips are connected.
Regarding Claims 5, 6, 13, 14, 21, 22, KANEKO discloses updating the first error evaluation information according to a decoding result of the second single-frame decoding in response to the second single-frame decoding being successful; and performing a fifth single-frame decoding on a third data frame read from a third physical unit in the physical units according to the updated first error evaluation information, wherein the third physical unit belongs to the physical unit group, and wherein the first physical unit belongs to a target physical unit, and the third physical unit belongs to a non- target physical unit for reducing a total number of UECC frames in the physical unit group.
[0061] As illustrated in FIG. 9, for example, in correspondence with writing a data frame into channels #1 to #10 in a distributed manner, the error correction circuit 100 of the memory system 1 according to the first embodiment includes 10 XOR restoration circuits 102 for performing XOR restoration on data of each channel. The error correction circuit 100 includes a total of 11 ECC decoders 101, that is, one ECC decoder 101 that performs ECC decoding on a data frame “Frame #0” generated from data of the channels #1 to #10, and 10 ECC decoders 101 that perform ECC decoding on a data frame “Frame #N” in which data of any of the channels is restored by the XOR restoration circuit 102.
Regarding Claims 7, 8, 15, 16, 23, 24, KANEKO discloses storing corrected third data frame in a fourth physical unit in the physical units in response to the fifth single-frame decoding being successful; adding the fourth physical unit to the physical unit group; and removing the third physical unit from the physical unit group, and updating a count value in response to a data frame read from any one of the physical units in the physical unit group being successfully decoded; determining that a default condition is satisfied in response to the count value reaching a critical value; and performing a multi-frame decoding in response to the default condition being satisfied.
[0063] FIG. 10 illustrates an error correction procedure by the error correction circuit 100 of the memory system 1. [0065] The error correction circuit 100 performs ECC decoding on the data frames “Frame #0” to “Frame #10” in a parallel manner (S204). The error correction circuit 100 determines whether there is a data frame for which error correction is successful (S205). When it is determined that there is a data frame for which error correction is successful (S205: Yes), the error correction circuit 100 outputs any one of data frames for which the corresponding error correction is successful (S206), and then terminates the corresponding error correction process on the assumption that the error correction is successful. Meanwhile, when it is determined that there is no data frame for which error correction is successful (S205: No), the error correction circuit 100 terminates the corresponding error correction process on the assumption that the error correction is failed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 14, 2026
Final Rejection 20260113
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV