DETAILED ACTION
This Office action is in response to the election filed 19 February 2026. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-7 and 15-20, in the reply filed on 19 February 2026 is acknowledged.
Claims 8-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 19 February 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 5 is objected to because of the following informalities: “that” in line 8 should be replaced with --than--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 15, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0226066 A1 to Young et al. (hereinafter “Young”).
Regarding independent claim 1, Young (Fig. 23) discloses a semiconductor structure comprising: nanosheets 116 (¶ 0049) separated by inner spacers 152 (between layers of 116; ¶ 0048), the inner spacers having a curved portion in a dimension (z-dimension; Fig. 23); source/drain regions 140 (¶ 0049) formed adjacent to the nanosheets; and gate material 154 (¶ 0049) formed on the nanosheets (Fig. 23).
Regarding claim 2, Young (Fig. 23) discloses the semiconductor structure of claim 1, wherein the curved portion of the inner spacers 152 is adjacent to the gate material 154.
Regarding claim 3, Young (Fig. 23) discloses the semiconductor structure of claim 1, wherein the gate material 154 is formed with a curved corner edge (Fig. 23).
Regarding claim 4, Young (Fig. 23) discloses the semiconductor structure of claim 1, wherein a curved corner edge of the gate material 154 comprises a complementary curvature to the curved portion of the inner spacers 152 (Fig. 23).
Regarding independent claim 15, Young (Fig. 23) discloses a transistor comprising:
nanosheets 116 (¶ 0049) separated by inner spacers 152 (between layers of 116, ¶ 0048), the inner spacers having a curved portion in a dimension (z-dimension; Fig. 23);
gate spacer material 232 (¶ 0035) formed adjacent to the nanosheets and the inner spacers;
source/drain regions 140 (¶ 0049) formed adjacent to the nanosheets 116; and
gate material 154 (¶ 0049) formed on the nanosheets (Fig. 23).
Regarding claim 18, Young (Fig. 23) discloses the transistor of claim 15, wherein a curved corner edge of the gate material 154 comprises a complementary curvature to the curved portion of the inner spacers 152 (Fig. 23).
Regarding claim 19, Young (annotated Fig. 23 below) discloses the transistor of claim 15, wherein the inner spacers 152 comprise a top-most inner spacer (labeled in Fig. 23 below) having a first thickness (labeled in Fig. 23 below) and other inner spacers 152 having a second thickness, the first thickness being less than the second thickness (Fig. 23).
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Regarding claim 20, Young (Fig. 23) discloses the transistor of claim 19, wherein the top-most inner spacer (labeled in Fig. 23 above) is adjacent to a top-most nanosheet (labeled in Fig. 23 above) of the nanosheets.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Young.
Regarding claim 5, Young (annotated Fig. 23 below) discloses the semiconductor structure of claim 1, wherein: the inner spacers 152 comprise a top-most inner spacer (labeled in Fig. 23 below) having a first thickness (labeled in Fig. 23 below) and other inner spacers 152 having a second thickness, the first thickness being less than the second thickness (Fig. 23); the top-most inner spacer 152 is adjacent to a top-most nanosheet 116 of the nanosheets and gate spacer material 232 (¶ 0035), the gate spacer material being formed adjacent to the gate material 154.
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In the instant embodiment, Young fails to expressly disclose: the top-most inner spacer comprises a first length in the dimension (z-dimension) less that a second length of the other inner spacers in the dimension. Young does disclose that length in the z-dimension of the layers (¶ 0018 - T1/T2) used to form the stack of nanosheets and inner spacers may be the same or different, and further that each layer of inner spacers may have different lengths (see ¶ 0018). Thus, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Moreover, it has been held that limitations directed to size and configuration are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 6-7 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Young as applied to claims 1 and 15 above, and further in view of US 2021/0305420 A1 to Frougier et al. (hereinafter “Frougier”).
Regarding claims 6 and 16, Young discloses the semiconductor structure of claim 1 and the transistor of claim 15, however fails to expressly disclose: wherein a stair-shaped portion of a substrate is formed below the source/drain regions and the gate material.
In the same field of endeavor, Frougier (Figs. 11A-C) discloses a semiconductor structure including a stair-shaped portion (Fig. 11B - spacer 710/712 formed thereon; ¶ 0058) of a substrate 102 (¶ 0034) formed below source/drain regions 904 (¶ 0068; labeled in Fig. 10C) and gate material 1112 (¶ 0073). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Young to include a stair-shaped portion as disclosed by Frougier for the purpose of providing isolation regions between semiconductor structures in an art-recognized manner, as exemplified by Frougier at ¶ 0046.
Regarding claims 7 and 17, Young and Frougier disclose the semiconductor structure of claim 6 and the transistor of claim 16, wherein a sidewall spacer 710/712 (¶ 0056) of silicon germanium material (¶¶ 0056, 32) is on the stair-shaped portion (Frougier, Fig. 11B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
1 April 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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