DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 and 9-11 in the reply filed on 04/02/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140008647 A1 – hereinafter Yamazaki) in view of Takemura (US 5581092 A – hereinafter Takemura).
Regarding independent claim 1, Yamazaki teaches:
(Original) A display device ([0225] – “A semiconductor device having a
display function (also referred to as a display device)”- hereinafter ‘DD’), comprising:
a first transistor (4010 – Fig. 12B – [0235] – “transistor 4010 provided in the
pixel portion 4002 is electrically connected to a display element to form a display panel”);
a pixel electrode (4034 – Fig. 12B – [0246] – “first electrode layer 4034 having
an opening pattern and serving as a pixel electrode”) electrically connected to the first transistor (4010 – Fig. 12B shows this); and
a second transistor (4011 – Fig. 12B – [0237] – “transistor 4011”) electrically
connected to the first transistor (4010),
wherein a nitrogen content per unit area of an active layer of the second
transistor is greater than a nitrogen content per unit area of an active layer of the first transistor.
Yamazaki does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Takemura teaches
wherein a nitrogen content per unit area of an active layer (608 – Fig. 8B –
{[16:8-10] – “the silicon film is patterned into a silicon island 607 for a peripheral circuit and another silicon island 608” – this is an active layer, {[16:56-57] – “concentration of oxygen in the channel region 618 is 5.times.10.sup.19 atoms/cm.sup.3”}, {([3:12-23] – “a conventional offset gate type TFT. Its active layer is roughly divided into three regions. The first region is an impurity region with a high impurity concentration (source and drain regions), designated by 13 and 17 in FIG. 2 (A). The second region is called an offset region or an LDD region, designated by reference numerals 14 and 16. The second region has a high resistance while it is substantially intrinsic or has the same conduction type as the source and drain regions in such a degree that the parasitic channel is suppressed. There is no gate electrode overlapping the second region. The third region is a channel forming region, designated by reference numeral 15” – channel regions are contained in active regions}) of the second transistor (Fig. 8B annotated, see below – hereinafter ‘T4’”) is greater than a nitrogen content per unit area of an active layer (607 – Fig. 8B – {[16:8-10] – “the silicon film is patterned into a silicon island 607 for a peripheral circuit and another silicon island 608” – this is an active layer}, {[16:54-56] – “concentration of the nitrogen, oxygen and carbon in the channel regions 616 and 617 is not higher than 1.times.10.sup.17 atoms/cm.sup.3”}) of the first transistor (Fig. 8B annotated, see below – hereinafter ‘T1’”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nitrogen content structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result [4:16-18] – “an active layer of a TFT is provided with a region having a larger band gap (Eg) by adding thereto an appropriate impurity such as oxygen, nitrogen or carbon.”
Regarding claim 2, Yamazaki as modified by Takemura, teaches claim 1 from which claim 2 depends. Yamazaki does not expressly disclose the limitations of claim 2.
However, in an analogous art, Takemura teaches
(Currently Amended) The display device of claim 1, wherein
the active layer of the first transistor (T1) comprises (607) a first channel region (617 – Fig. 8C – [16:52-53] – “channel regions 616, 617 and 618 are defined at the same time”), the active layer (608) of the second transistor (T4) comprises a second channel region (618 – Fig. 8C – [16:52-53] – “channel regions 616, 617 and 618 are defined at the same time”), and
a nitrogen content per unit area ([16:54-56] – “concentration of oxygen in the channel region 618 is 5.times.10.sup.19 atoms/cm.sup.3”) of the second channel region (618) is greater than a nitrogen content per unit area of the first channel region (616 – [16:54-56] – “concentration of the nitrogen, oxygen and carbon in the channel regions 616 and 617 is not higher than 1.times.10.sup.17 atoms/cm.sup.3”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transistor structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor with nitrogen content as stated above in claim 1.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 3, Yamazaki as modified by Takemura, teaches claim 1 from which claim 3 depends. Yamazaki does not expressly disclose the limitations of claim 3.
However, in an analogous art, Takemura teaches
(Currently Amended) The display device of claim 1, wherein
the active layer (607) of the first transistor (T1) comprises a first source region and a first drain region ([3:12-23] – “a conventional offset gate type TFT. Its active layer is roughly divided into three regions. The first region is an impurity region with a high impurity concentration (source and drain regions), designated by 13 and 17 in FIG. 2 (A). The second region is called an offset region or an LDD region, designated by reference numerals 14 and 16. The second region has a high resistance while it is substantially intrinsic or has the same conduction type as the source and drain regions in such a degree that the parasitic channel is suppressed. There is no gate electrode overlapping the second region. The third region is a channel forming region, designated by reference numeral 15” – source and drain regions are contained in active regions),
the active layer (608) of the second transistor (T4) comprises a second source region and a second drain region, and
a nitrogen content per unit area of the second source region is greater than a nitrogen content per unit area of the first source region ([Claim 21] – “wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transistor structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor with nitrogen content as stated above in claim 1.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 4, Yamazaki as modified by Takemura, teaches claim 3 from which claim 4 depends. Yamazaki does not expressly disclose the limitations of claim 4.
However, in an analogous art, Takemura teaches
(Original) The display device of claim 3, wherein a nitrogen content per unit
area of the second drain region is greater than a nitrogen content per unit area of the first drain region ({[Claim 21] – “wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors”} – {[3:12-23] – “a conventional offset gate type TFT. Its active layer is roughly divided into three regions. The first region is an impurity region with a high impurity concentration (source and drain regions), designated by 13 and 17 in FIG. 2 (A). The second region is called an offset region or an LDD region, designated by reference numerals 14 and 16. The second region has a high resistance while it is substantially intrinsic or has the same conduction type as the source and drain regions in such a degree that the parasitic channel is suppressed. There is no gate electrode overlapping the second region. The third region is a channel forming region, designated by reference numeral 15” – channel regions are contained in active regions).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nitrogen content structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor with nitrogen content as stated above in claim 1.
Regarding claim 4, Yamazaki as modified by Takemura, teaches claim 3 from which claim 4 depends. Yamazaki teaches
(Currently Amended) The display device of claim 1, wherein
the active layer of the first transistor (4010) comprises a first active layer
overlapping (403 – Fig. 3A – [0096] – “stack 403 of oxide semiconductor layers – this corresponds to an active layer) a first gate electrode (401 – Fig. 3A – [0075] – “gate electrode layer 401”) of the first transistor (4010) in a plan view (Fig. 3B annotated, see below, shows this),
the active layer of the second transistor (4010) comprises a second
active layer overlapping a second gate electrode of the second transistor in a plan view (Fig. 12A shows the structure with two transistors), and
a nitrogen content per unit area of the second active layer is greater
than the nitrogen content per unit area of the first active layer.
Yamazaki does not expressly disclose the other limitations of claim 4.
However, in an analogous art, Takemura teaches
a nitrogen content per unit area of the second active layer (608) is greater
than the nitrogen content per unit area of the first active layer (607 – [Claim 21] – “wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nitrogen content structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor with nitrogen content as stated above in claim 1.
Regarding claim 6, Yamazaki as modified by Takemura, teaches claim 5 from which claim 6 depends. Yamazaki does not expressly disclose the limitations of claim 6.
However, in an analogous art, Takemura teaches
(Currently Amended) The display device of claim 5, wherein the first
active layer (607) and the second active layer (608) are disposed on a same layer (Fig. 8B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nitrogen content structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor as stated above in claim 2.
Regarding claim 7, Yamazaki as modified by Takemura, teaches claim 1 from which claim 7 depends. Yamazaki does not expressly disclose the limitations of claim 7.
However, in an analogous art, Takemura teaches
(Original) The display device of claim 1, wherein a threshold voltage
([14:14-15] – “threshold voltage of the TFT is 0.5-2 V in the case of NMOS”) of the second transistor (T4 – [13:66-67 and 14:1-2] – “an NMOS TFT may be connected to the PMOS TFT in series in the pixel region. Of course, two PMOS TFTs may be used in parallel in the pixel region” – T4 contains 618 that is the single NMOS transistor) is greater than a threshold voltage ([14:14-16] – “threshold voltage of the TFT is … -0.5--3 V in the case of PMOS”) of the first transistor (T1 – [13:66-67 and 14:1-2] – “an NMOS TFT may be connected to the PMOS TFT in series in the pixel region. Of course, two PMOS TFTs may be used in parallel in the pixel region” – T1 contains 617 that is the single NMOS transistor).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the threshold voltage as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of [13:5-11] – “the channel region is added with oxygen, nitrogen, carbon or the like, there is a tendency that a threshold voltage is shifted. For example, when adding oxygen into the channel region, 1-10% of the added oxygen becomes donor and the conductivity becomes a weak N-type. Accordingly, the threshold voltage shifts to a positive side either in the NTFT or PTFT.”
Regarding claim 8, Yamazaki as modified by Takemura, teaches claim 1 from which claim 8 depends. Yamazaki teaches
(Currently Amended) The display device of claim 1, wherein each of
the active layer (403a – [0101] – “oxide semiconductor layer 403a”) of the first transistor (4010) and the active layer (403a – both transistors contain the same active layer structure) of the second transistor (4011) further comprises at least one of indium-gallium-zinc oxide and indium-gallium-zinc-tin oxide ([0101] – “oxide semiconductor layer 403a, an In--Ga--Zn-based oxide film” – transistors 4010 and 4011 are formed the same way as the transistor containing 403a).
Regarding independent claim 9, Yamazaki teaches:
(Currently Amended) A display device ([0225] – “A semiconductor
device having a display function (also referred to as a display device)”- hereinafter ‘DD’), comprising:
an active layer (403 – Fig. 3A – [0096] – “stack 403 of oxide semiconductor
layers – this corresponds to an active layer);
a first transistor (4010 – Fig. 12B – [0235] – “transistor 4010 provided in the
pixel portion 4002 is electrically connected to a display element to form a display panel”) comprising a first gate electrode (401 – Fig. 3A – [0075] – “gate electrode layer 401”) overlapping a first channel region (Fig. 12B annotated, see below – hereinafter ‘403-4010’) of the active layer (403) in the plan view (Fig. 11B shows this);
a second transistor (4011 – Fig. 12B – [0237] – “transistor 4011”) comprising a second gate electrode (Fig. 12B annotated, see below – [0075] – “gate electrode layer 401” – hereinafter 401-4011) overlapping a second channel region (Fig. 12B annotated, see below – hereinafter ‘403-4011’) of the active layer (403) in plan view (Fig. 11B shows this); and
a pixel electrode (4034 – Fig. 12B – [0246] – “first electrode layer 4034 having an opening pattern and serving as a pixel electrode”) electrically connected to the first transistor (4010 – Fig. 12B shows this),
wherein a nitrogen content per unit area of the second channel region is greater than a nitrogen content per unit area of the first channel region.
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Yamazaki does not expressly disclose the other limitations of claim 9.
However, in an analogous art, Takemura teaches
wherein a nitrogen content per unit area ([16:54-56] – “concentration of oxygen in the channel region 618 is 5.times.10.sup.19 atoms/cm.sup.3”) of the second channel region (618 – Fig. 8C – [16:52-53] – “channel regions 616, 617 and 618 are defined at the same time”) is greater than a nitrogen content per unit area (616 – [16:54-56] – “concentration of the nitrogen, oxygen and carbon in the channel regions 616 and 617 is not higher than 1.times.10.sup.17 atoms/cm.sup.3”) of the first channel region (617 – Fig. 8C – [16:52-53] – “channel regions 616, 617 and 618 are defined at the same time”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nitrogen content structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 10, Yamazaki as modified by Takemura, teaches claim 9 from which claim 10 depends. Yamazaki does not expressly disclose the limitations of claim 10.
However, in an analogous art, Takemura teaches
(Original) The display device of claim 9, wherein
the active layer (607) comprises:
a first source region ([3:12-23] – “a conventional offset gate type TFT. Its
active layer is roughly divided into three regions. The first region is an impurity region with a high impurity concentration (source and drain regions), designated by 13 and 17 in FIG. 2 (A). The second region is called an offset region or an LDD region, designated by reference numerals 14 and 16. The second region has a high resistance while it is substantially intrinsic or has the same conduction type as the source and drain regions in such a degree that the parasitic channel is suppressed. There is no gate electrode overlapping the second region. The third region is a channel forming region, designated by reference numeral 15” – source and drain regions are contained in active regions) of the first transistor (Fig. 8B annotated, see below – hereinafter ‘T1’”);
a first drain region of the first transistor (T1);
a second source region of the second transistor (Fig. 8B annotated,
see below – hereinafter ‘T2’”); and
a second drain region of the second transistor (T2), and
a nitrogen content per unit area of the second source region is greater than
a nitrogen content per unit area of the first source region ([Claim 21] – “wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transistor structure as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor with nitrogen content as stated above in claim 2.
Regarding claim 11, Yamazaki as modified by Takemura, teaches claim 10 from which claim 11 depends. Yamazaki does not expressly disclose the limitations of claim 11.
However, in an analogous art, Takemura teaches
(Original) The display device of claim 10, wherein a nitrogen content per
unit area of the second drain region ([3:12-23] – “a conventional offset gate type TFT. Its active layer is roughly divided into three regions. The first region is an impurity region with a high impurity concentration (source and drain regions), designated by 13 and 17 in FIG. 2 (A). The second region is called an offset region or an LDD region, designated by reference numerals 14 and 16. The second region has a high resistance while it is substantially intrinsic or has the same conduction type as the source and drain regions in such a degree that the parasitic channel is suppressed. There is no gate electrode overlapping the second region. The third region is a channel forming region, designated by reference numeral 15” – source and drain regions are contained in active regions) is greater than a nitrogen content per unit area of the first drain region ([Claim 21] – “wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nitrogen content as taught by Takemura into Yamazaki.
An ordinary artisan would have been motivated to use the known technique of Takemura in the manner set forth above to produce the predictable result of a transistor with nitrogen content as stated above in claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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