Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10, 12-13, and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamaki et al (2020/0004071) hereinafter, Tamaki.
In regards to claim 1, Tamaki teaches a display panel comprising: a first emitting part, a second emitting part, and a third emitting part arranged along a first direction (fig. 2, PE1,PE2, PE3 along X direction) and (fig. 15 PE left to right in X direction ;
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the driving circuit, or a first transistor, a second transistor, and a third transistor spaced apart from the first, second, and third emitting parts in the first direction, and arranged along the first direction; and [116-120]
[0116] The pixel circuit PC comprises three switch portions SW1 to SW3 and a latch portion LT. The switch portion SW1 is formed from, for example, a single n-channel MOS transistor. The switch portion SW1 includes one end electrically connected to a signal line SL and another end electrically connected to the latch portion LT. The ON/OFF operation of the switch portion SW1 is controlled by a scanning signal supplied from a scanning line GL. That is, the switch portion SW1 is placed in an ON (closed) state by applying a scanning signal φV via the scanning line GL from the scanning-line driving circuit included in the peripheral circuit Cr2 or Cr4 shown in FIG. 1, thus capturing the data (the signal potential corresponding to gradation) SIG supplied via the signal line SL from the signal line driving circuit included in the peripheral circuit Cr1 or Cr3 shown in FIG. 1.
a first connection wiring, a second connection wiring, and a third connection wiring each extending along the first direction (fig. 2 RL1, RL2, and RL3) Tamaki and connecting the first, second, and third emitting parts to the first, second, and third transistors, (fig. 8 EC, PE, RL))
wherein the first, second, and third connection wirings include:
a first emission connection part, a second emission connection part, and a third emission connection part each connected to a corresponding emitting part among the first, second, and third emitting parts; and (fig. 3 CTb for each pixel) Tamaki
a first driver connection part, a second driver connection part, and a third driver connection part each connected (fig. 3 Cta for example pixel) Tamaki to a corresponding transistor among the first, second, and third transistors (fig. 8 SW1, SW2, and SW3) [0115-118], and
an arrangement order of the first, second, and third emission connection parts arranged along the first direction (fig. 10 and 15 Ctb arrange along X direction for each Px) Tamaki and an arrangement order of the first, second, and third driver connection parts arranged along the first direction are same as each other (fig. 10 corresponding CTa arranged along X direction) Tamaki.
In regards to claim 16, Tamaki teaches a display panel comprising (abstract):
a plurality of pixels including first group pixels and second group pixels, the first and second group pixels including (fig. 2 PE1 and PE2 for example: emitting parts (fig. 2 Pixel electrodes), and driving transistors connected to the emitting parts ([116] fig. 8 SW1-SW3 for each PC); and
a driving circuit that provides an electrical signal to each of the plurality of pixels([116] fig. 8 SW1-SW3 for each PC);, and
overlaps at least some of the emitting parts of the plurality of pixels in a plan view (fig. 2 PC2/PC1 are at least overlapped by PE2), wherein the emitting parts of the first group pixels overlap the driving circuit (fig. 2 PE1 overlaps Cr1(Dr)), the emitting parts of the second group pixels are spaced apart from the driving circuit (fig. 2 PE2 has offset for PC2), the first group pixels includes connection wirings (fig. 2 RL1), the connection wirings including: emission connection parts connected to the emitting parts of the first group pixels (fig. 3 CTb1), and driver connection parts connected to the driving transistors of the first group pixels (fig. 3 CTa1 and fig. 8 transistors), and an arrangement order of the driving transistors of the first group pixels arranged along a first direction (fig. 10 and 15 Ctb arrange along X direction for each Px) Tamaki and an arrangement order of the emission connection parts of the first group pixels arranged in the first direction are same as each other. (fig. 10 corresponding CTa arranged along X direction) Tamaki.
In regards to claim 2, Tamaki teaches display panel of claim 1, wherein the first, second, and third emission connection parts are arranged along the first direction. (fig. 10 and 15 Ctb arrange along X direction for each Px) Tamaki
In regards to claim 3, Tamaki teaches display panel of claim 2, further comprising: a fourth emitting part, a fifth emitting part, and a sixth emitting part different from the first, second, and third emitting parts; a fourth transistor, a fifth transistor, and a sixth transistor different from the first, second, and third transistors; a fourth connection wiring, a fifth connection wiring, and a sixth connection wiring spaced apart from the first, second, and third connection wirings in a plan view, and respectively connecting the fourth, fifth, and sixth emitting parts to the fourth, fifth, and sixth transistors, wherein the fourth, fifth, and sixth connection wirings include: a fourth emission connection part, a fifth emission connection part, and a sixth emission connection part respectively connected to the fourth, fifth, and sixth emitting parts; and a fourth driver connection part, a fifth driver connection part, and a sixth driver connection part respectively connected to the fourth, fifth, and sixth transistors, and the fourth, fifth, and sixth emission connection parts are arranged along the first direction (fig. 10 bottom row for example 4-6 emission connection part and corresponding 4-6 driver connection part) Tamaki.
In regards to claim 4, Tamaki teaches display panel of claim 3, wherein: the fourth, fifth, and sixth transistors are spaced apart from the first, second, and third transistors in the first direction; and the first, second, and third emission connection parts and the fourth, fifth, and sixth emission connection parts do not overlap each other in the first direction. (fig. 10 bottom row for example 4-6 emission connection part and corresponding 4-6 driver connection part) Tamaki.
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In regards to claim 5, Tamaki teaches display panel of claim 4, wherein the first, second, and third driver connection parts are arranged along the first direction, and the fourth, fifth, and sixth driver connection parts are arranged along the first direction.(fig. 10 CTAs corresponding along X direction) Tamaki
In regards to claim 6, Tamaki teaches display panel of claim 5, wherein among the first, second, third, fourth, fifth, and sixth connection wirings, the first, second, and third connection wirings extend in an opposite direction with respect to the fourth, fifth, and sixth connection wirings and the fourth, fifth, and sixth driver connection parts (fig. 10 RL bottom extend down on the bottom section and RL extends up for the top section of PX1))
In regards to claim 7, Tamaki teaches display panel of claim 3, wherein an arrangement order of the first, second, third, fourth, fifth, and sixth emission connection parts arranged in the first direction ((fig. 10 PX CTB along X direction) Tamaki) and an arrangement order of the first, second, third, fourth, fifth, and sixth transistors arranged in the first direction are same as each other (fig. SW1-SW3 for ((fig. 10 PX CTB along X direction) Tamaki).
In regards to claim 8, Tamaki teaches display panel of claim 3, wherein the first, second, and third driver connection parts are respectively spaced apart from the fourth, fifth, and sixth driver connection parts in a second direction intersecting the first direction.(fig. 10 CTb and Cta offset in Y direction) Tamaki
In regards to claim 9, Tamaki teaches display panel of claim 8, wherein light emitted by the first light emitting part and light emitted by the fourth light emitting part have different colors from each other (fig. 12 PE31-PE33 are blue and PE41 is W) Tamaki.
In regards to claim 10, Tamaki teaches display panel of claim 9, wherein an arrangement order of the first, second, and third emitting parts and an arrangement order of the fourth, fifth, and sixth emitting parts are same as each other (fig. 12 (PE33, PE32, PE31 and arrangement of PE41, PE42, and PE43) Tamaki.
In regards to claim 12, Tamaki teaches display panel of claim 1, further comprising: a driving circuit overlapping the first, second, and third emitting parts in a plan view, the driving circuit that provides an electrical signal to each of the first, second, and third emitting parts, wherein the first, second, and third transistors are spaced apart from the driving circuit. (fig. 2 CR1(Dr) overlapping first three PEs) Tamaki
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In regards to claim 13, Tamaki teaches display panel of claim 1, wherein each of the first, second, and third emitting parts comprises: a first electrode, a second electrode disposed on the first electrode, and an emission connection part, and the emission connection part is connected to the second electrode (fig. 4 CTb1 to fig. 5 CTa1 for reach emitting parts in fig. 2 ) [0046-0053].
In regards to claim 15, Tamaki teaches display panel of claim 1, wherein each of the first, second, and third transistors is an N-type transistor [116] n-channel MOS transistors).
In regards to claim 17, Tamaki teaches display panel of claim 16, wherein each of the connection wirings of the first group pixels is disposed in a space between the emission connection parts of the first group pixels and the driver connection parts of the first group pixels (fig. 2 (RL1)).
In regards to claim 18, Tamaki teaches display panel of claim 16, wherein each of the connection wirings of the first group pixels has a multi-layered structure (fig. 5 RL1 is on one layer and extends down towards CTa1)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaki in view of Yo (2004/0189571) hereinafter, Yo.
In regards to claim 11, Tamaki teaches the display panel of claim 9, further comprising: (fig. 22 (PX1 offset) a seventh emitting part, an eighth emitting part, and a ninth emitting part (fig. 22 for example PE elements from left to right appear to be 24 in all per row) spaced apart from the first, second, and third emitting parts in the first direction; a tenth emitting part, an eleventh emitting part, and a twelfth emitting part spaced apart from the fourth, fifth, and sixth emitting parts in the first direction (fig. 22 top row of Pes) and respectively spaced apart from the seventh, eighth, and ninth emitting parts in the second direction; a seventh transistor, an eighth transistor, and a ninth transistor overlapping the seventh, eighth, and ninth emitting parts in a plan view (fig. top row at least two columns of PEs offset), respectively connected to the seventh, eighth, and ninth emitting parts, and arranged along the first direction [194-200]; and a tenth transistor, an eleventh transistor, and a twelfth transistor overlapping the tenth, eleventh, and twelfth emitting parts in a plan view (fig. 8 SW1-SW3 for each emitter), respectively connected to the tenth, eleventh, and twelfth emitting parts, and arranged along the first direction [194-0200],
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Tamaki fails to teach wherein the seventh emitting part and the tenth emitting part emit a same color light.
However, Yo teaches seventh emitting part and the tenth emitting part emit a same color light.(fig. 3 R, G, B, and R).
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Tamaki to further include seventh emitting part and the tenth emitting part emit a same color light as taught by Yo in order to a well known color scheme that can lower manufacturing cost and provide color display.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaki in view of Yo (2004/0189571) hereinafter, Yo.
In regards to claim 14. The display panel of claim 13, wherein: the second electrodes of the respective first, second, and third emitting parts are separated from each other (fig. 8 EC for each pixel); and
Tamaki fails to teach each of the second electrodes is a cathode of each of the first, second, and third emitting parts.
However, Kim teaches each of the second electrodes is a cathode of each of the first, second, and third emitting parts. (fig. 4b connected to cathode of light emitting part).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Tamaki to further include each of the second electrodes is a cathode of each of the first, second, and third emitting parts as taught by Kim through simple substitution of one for the other and the results would have performed equally well at driving the light emitting element.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaki in view of further in view of Kim et al 2007/0194307, hereinafter, Kim2 further in view of Kim et al (2018/0175009) hereinafter, Kim.
In regards to claim 19, Tamaki fails to teach the display panel of claim 16, wherein each of the emitting parts of the plurality of pixels comprises: an anode, a cathode disposed on the anode, and an emitting part disposed between the anode and the cathode, and
However, Kim2 teaches wherein each of the emitting parts of the plurality of pixels comprises: an anode, a cathode disposed on the anode, and an emitting part disposed between the anode and the cathode (fig. 2b 244 cathode on top with EML in middle and 241 anode on bottom), and
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Tamaki and Kim2 to further include wherein each of the emitting parts of the plurality of pixels comprises: an anode, a cathode disposed on the anode, and an emitting part disposed between the anode and the cathode as taught by Kim2 in order to
Tamaki and Kim2 fail to teach each of the driving transistors of the plurality of pixels is connected to the cathode.
However, Kim teaches each of the driving transistors of the plurality of pixels is connected to the cathode. (fig. 4b connected to cathode of light emitting part).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Tamaki to further each of the driving transistors of the plurality of pixels is connected to the cathode as taught by Kim through simple substitution of one for the other and the results would have performed equally well at driving the light emitting element.
Claim(s) 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaki in view of Wu et al 2019/0122599 hereinafter, Wu
In regards to claim 20, Tamaki fails to teach display panel of claim 16, wherein the arrangement order of the driving transistors of the first group pixels arranged in the first direction is different from each other in adjacent rows.
However, Wu teaches wherein the arrangement order of the driving transistors of the first group pixels arranged in the first direction is different from each other in adjacent rows.(fig. 7 R, G, B, W in first row and B, W, R, G in second row) Wu.
It would have been obvious to one of ordinary skill in the art to modify the teachings of Tamaki to further include wherein the arrangement order of the driving transistors of the first group pixels arranged in the first direction is different from each other in adjacent rows as taught by Wu in order to reduce flickering [004] and help reduce visual artifacts by alternating color elements.
In regards to claim 21, Tamaki in view of Wu teaches, see rational of claim 20, the display panel of claim 16, wherein an arrangement order of the driving transistors of the second group pixels arranged in the first direction is different from the arrangement order of the driving transistors of the first group pixels arranged in the first direction. .(fig. 7 R, G, B, W in first row and B, W, R, G in second row) Wu.
Conclusion
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/GRANT SITTA/Primary Examiner, Art Unit 2622
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