DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14, in the reply filed on 5/17/2026 is acknowledged.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Rejection 1/2
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sim et al. (US 2012/0058639).
(Re Claim 1) Sim teaches a memory device, comprising: cell plugs (430+425 visible in cross-section VII-VII’; Fig. 24B); an insulating pattern (110; Fig. 24B) disposed on the cell plugs and including openings (Fig. 24B markup) corresponding to the cell plugs; bit lines (the part of 150a in cross-section VII-VII’ above the dashed line in the Fig. 24B markup) disposed on the insulating pattern; bit line contacts (the parts of 150a+150c+435 in cross-section VII-VII’ below the dashed line in the Fig. 24B markup) disposed in the openings to couple the cell plugs and the bit lines; first air gaps (the portions of the pairs of 160 immediately adjacent to each bit line in the Fig. 24B markup) disposed between the bit lines; and second air gaps (the portions of the pairs of 160 immediately adjacent to each bit line in the Fig. 24B markup) extending from the first air gaps and enclosed by the bit line contacts and the insulating pattern (Fig. 24B).
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(Re Claim 3) Sim teaches the memory device according to claim 1, wherein each of the bit line contacts comprises: an upper bit line contact (Fig. 24B markup) extending from each of the bit lines; and a lower bit line contact (Fig. 24B markup) contacting a lower surface (lowermost surface; Fig. 24B) of the upper bit line contact (Fig. 24B).
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(Re Claim 5) Sim teaches the memory device according to claim 3, wherein the upper bit line contact has a width (left to right) equal to a width (left to right) of each of the bit lines (Fig. 24B).
(Re Claim 6) Sim teaches the memory device according to claim 3, wherein the upper bit line contact contacts a portion (upper left part; Fig. 24B) of an inner wall of each of the openings (Fig. 24B).
(Re Claim 7) Sim teaches the memory device according to claim 3, wherein the lower bit line contact fills a lower portion (coextensive with the lower bit line contact; Fig. 24B) of each of the openings.
(Re Claim 8) Sim teaches the memory device according to claim 3, wherein each of the second air gaps is enclosed by a corresponding one of the first air gaps (nearest to each second air gap; Fig. 24B), a sidewall (from left to right, the left sidewall of each upper bit line contact; Fig. 24B) of the upper bit line contact, an inner wall (from left to right, the left wall of the openings; Fig. 24B) of a corresponding one of the openings, and an upper surface (from left to right, the left surface of 435 that is not covered by 150a; Fig. 24B) of the lower bit line contact.
(Re Claim 9) Sim teaches the memory device according to claim 1, further comprising a capping layer (155; Fig. 24B) covering upper surfaces of the bit lines and extending in a horizontal direction (left to right; Fig. 24B).
(Re Claim 10) Sim teaches the memory device according to claim 9, wherein the capping layer is an oxide layer (silicon oxide; ¶60).
(Re Claim 11) Sim teaches the memory device according to claim 9, wherein the first air gaps are enclosed by the capping layer, sidewalls of the bit lines (from left to right; the left, right, left, and then right sidewalls of the bit lines; Fig. 24B), an upper surface of the insulating pattern (topmost surface; Fig. 24B), and the second air gaps (Fig. 24B).
(Re Claim 12) Sim teaches the teaches the memory device according to claim 1, wherein each of the first air gaps partially overlaps the insulating pattern (Fig. 24B).
(Re Claim 13) Sim teaches the memory device according to claim 1, wherein each of the first air gaps extends in a direction (left to right; Fig. 24B) in which each of the bit lines extends.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Sim et al. (US 2012/0058639) as respectively applied to claims 1 and 3 above, and further in view of Sharangpani et al. (US 2023/0352401).
(Re Claim 2) Sim teaches the memory device according to claim 1, but has not been explicitly shown to teach the memory device wherein the bit lines are comprised of molybdenum.
Sharangpani teaches forming bit lines using molybdenum (¶281).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it form the bit lines of Sim using molybdenum as taught by Sharangpani as molybdenum has a high electrical conductivity (Sharangpani: ¶281).
(Re Claim 4) Sim teaches the memory device according to claim 3, but has not been explicitly shown to teach the memory device wherein the upper bit line contact is comprised of molybdenum.
Sharangpani teaches forming an upper bit line contact (lower part of 118) using molybdenum (¶281).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it form the upper bit line contacts of Sim using molybdenum as taught by Sharangpani as molybdenum has a high electrical conductivity (Sharangpani: ¶281).
Rejection 2/2
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gupta et al. (US 2022/0051930).
(Re Claim 1) Gupta teaches a memory device, comprising: cell plugs (center and right 104 in Fig. 1E); an insulating pattern (102; Fig. 1E) disposed on the cell plugs and including openings (Fig. 1E markup) corresponding to the cell plug; bit lines (part of 122 shown in the Fig. 1E markup; ¶46) disposed on the insulating pattern; bit line contacts (110+114+lower part of 122 shown in the Fig. 1E markup) disposed in the openings to couple the cell plugs and the bit lines (Fig. 1E); first air gaps (each portion of each pair of air gap immediately adjacent to each bit line as seen in the Fig. 1E markup) disposed between the bit lines; and second air gaps (each portion of each pair of air gap immediately adjacent to each bit line as seen in the Fig. 1E markup) extending from the first air gaps and enclosed by the bit line contacts and the insulating pattern (Fig. 1E).
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(Re Claim 2) Gupta teaches the memory device according to claim 1, wherein the bit lines are comprised of molybdenum (material 116, formed into 122, is made of molybdenum; ¶42).
(Re Claim 3) Gupta teaches the memory device according to claim 1, wherein each of the bit line contacts comprises: an upper bit line contact (part of 122 that is not the bit line; Fig. 1E markup) extending from each of the bit lines; and a lower bit line contact (remaining part of bit line contacts) contacting a lower surface (lowermost surface; Fig. 1E) of the upper bit line contact.
(Re Claim 4) Gupta teaches the memory device according to claim 3, wherein the upper bit line contact is comprised of molybdenum (material 116, formed into 122, is made of molybdenum; ¶42).
(Re Claim 5) Gupta teaches the memory device according to claim 3, wherein the upper bit line contact has a width (left to right) equal to a width (left to right) of each of the bit lines (Fig. 1E).
(Re Claim 7) Gupta teaches the memory device according to claim 3, wherein the lower bit line contact fills a lower portion (the portion coextensive with the lower half of the part of 114 that is between the top of 102 and the bottom of 130 within each opening; Fig. 1E) of each of the openings.
(Re Claim 8) Gupta teaches the memory device according to claim 3, wherein each of the second air gaps is enclosed by a corresponding one of the first air gaps (nearest to each second air gap; Fig. 1E), a sidewall (from left to right, the left sidewall of each upper bit line contact) of the upper bit line contact, an inner wall (in order from left to right, the leftmost wall of each opening in Fig. 1E) of a corresponding one of the openings, and an upper surface (from left to right, the left upper surface of each lower bit line contacts 110 that are not covered by 114; Fig. 1E) of the lower bit line contact.
(Re Claim 9) Gupta teaches the memory device according to claim 1, further comprising a capping layer (130; Fig. 1E) covering upper surfaces of the bit lines and extending in a horizontal direction (left to right; Fig. 1E).
(Re Claim 10) Gupta teaches the memory device according to claim 9, wherein the capping layer is an oxide layer (e.g., SiOx; ¶57).
(Re Claim 11) Gupta teaches the memory device according to claim 9, wherein the first air gaps are enclosed by the capping layer (Fig. 1E), sidewalls (left or right sidewalls; Fig. 1E) of the bit lines (Fig. 1E), an upper surface (the entire upper surface of 102 that follows the contour of the elements 108 and the parts of 102 between them; Fig. 1E) of the insulating pattern, and the second air gaps (Fig. 1E).
(Re Claim 12) Gupta teaches the memory device according to claim 1, wherein each of the first air gaps partially overlaps the insulating pattern (Fig. 1E).
(Re Claim 13) Gupta teaches the memory device according to claim 1, wherein each of the first air gaps extends in a direction (left to right; Fig. 1E) in which each of the bit lines extends.
(Re Claim 14) Gupta teaches the memory device according to claim 1, wherein the bit line contacts and the second air gaps are positioned in the openings (Fig. 1E markup).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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