DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed May 27, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed March 11, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et.al. (US 20210249627 A1), hereinafter Lee.
Regarding claim 1, Lee teaches a display device (Fig 1 display device 1, [0056]) comprising: a substrate (Fig 9 substrate 110, [0122]) including a display region (See annotated figure; Examiner interprets the display region as shown) and a non-display region (See annotated figure; Examiner interprets the non-display region as shown) adjacent to the display region (See annotated figure) in a first horizontal direction (Fig 9 direction DR2); a light-emitting element layer (Fig 9 light emitting layer EML, [0122]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) being in the display region (See annotated figure); a thin-film substrate (Fig 9 circuit board 60, [0150]) connected to the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the thin-film substrate (Fig 9 circuit board 60, [0150]) being in (Examiner notes the limitation does not require the entirety of the thin-film substrate to be in the non-display region) the non-display region (See annotated figure); a first semiconductor chip (Fig 9 display driving circuit 40, [0150]) on a lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) being in (Examiner notes the limitation does not require the entirety of the first semiconductor chip to be in the non-display region) the non-display region (See annotated figure), at least a portion of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) overlapping (See annotated figure; shaded area) with the thin-film substrate (Fig 9 circuit board 60, [0150]) in a vertical direction (Fig 9 direction DR3); a first through-via (Fig 9 through hole OP1, [0126]) in the non-display region (See annotated figure), the first through-via (Fig 9 through hole OP1, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the first through-via (Fig 9 through hole OP1, [0126]) electrically connecting ([0150]) the thin-film substrate (Fig 9 circuit board 60, [0150]) and the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) to each other; and a partitioning wall (Fig 9 sealing member 30, [0134]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the partitioning wall (Fig 9 sealing member 30, [0134]) being in the display region (See annotated figure), the partitioning wall (Fig 9 sealing member 30, [0134]) surrounding a sidewall (Fig 9) of the light-emitting layer (Fig 9 light emitting layer EML, [0122]).
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Regarding claim 2, Lee teaches the substrate (Fig 9 substrate 110, [0122]) includes silicon (Si) (glass is SiO2, [0125]).
Regarding claim 3, Lee teaches a molding layer (Fig 9 under-panel member 50, [0079]) on the lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the molding layer (Fig 9 under-panel member 50, [0079]) surrounding a sidewall (Fig 9) of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]).
Regarding claim 4, Yang teaches a sidewall of the substrate (Fig 9 substrate 110, [0122]) is aligned (See annotated figure; shaded area) with a sidewall of the molding layer (Fig 9 under-panel member 50, [0079]) in the vertical direction (Fig 9 direction DR3).
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Regarding claim 5, Lee teaches a lower surface of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) is coplanar (the thickness of the under-panel member is the same as the driving circuit 40, [0080]) with a lower surface of the molding layer (Fig 9 under-panel member 50, [0079]).
Regarding claim 13, Lee teaches a display device (Fig 1 display device 1, [0056]) comprising: a substrate (Fig 9 substrate 110, [0122]) including silicon (Si) (glass is SiO2, [0125]), the substrate (Fig 9 substrate 110, [0122]) including a display region (See annotated figure; Examiner interprets the display region as shown) and a non-display region (See annotated figure; Examiner interprets the non-display region as shown) adjacent to the display region (See annotated figure) in a first horizontal direction (Fig 9 direction DR2); a light-emitting element layer (Fig 9 light emitting layer EML, [0122]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) being in the display region (See annotated figure); a thin-film substrate (Fig 9 circuit board 60, [0150]) connected to the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the thin-film substrate (Fig 9 circuit board 60, [0150]) spaced apart from (Fig 9) the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) in a horizontal direction (Fig 9 direction DR2), the thin-film substrate (Fig 9 circuit board 60, [0150]) being in (Examiner notes the limitation does not require the entirety of the thin-film substrate to be in the non-display region) the non-display region (See annotated figure); a first semiconductor chip (Fig 9 display driving circuit 40, [0150]) on a lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) being in (Examiner notes the limitation does not require the entirety of the first semiconductor chip to be in the non-display region) the non-display region (See annotated figure), at least a portion of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) overlapping with (See annotated figure; shaded area) the thin-film substrate (Fig 9 circuit board 60, [0150]) in a vertical direction (Fig 9 direction DR3); a molding layer (Fig 9 under-panel member 50, [0079]) on the lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the molding layer (Fig 9 under-panel member 50, [0079]) surrounding a sidewall (Fig 9) of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]); a first through-via (Fig 9 through hole OP1, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the first through-via (Fig 9 through hole OP1, [0126]) in the non-display region (See annotated figure), the first through-via (Fig 9 through hole OP1, [0126]) electrically connecting ([0150]) the thin-film substrate (Fig 9 circuit board 60, [0150]) and the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) to each other; and a partitioning wall (Fig 9 sealing member 30, [0134]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the partitioning wall (Fig 9 sealing member 30, [0134]) being in the display region (See annotated figure), the partitioning wall (Fig 9 sealing member 30, [0134]) surrounding a sidewall (Fig 9) of the light-emitting layer (Fig 9 light emitting layer EML, [0122]).
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Regarding claim 14, Lee teaches a second through-via (Fig 9 through hole OP2, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the second through-via (Fig 9 through hole OP2, [0126]) spaced apart from (Fig 9) the first through-via (Fig 9 through hole OP1, [0126]) in the horizontal direction (Fig 9 direction DR2), the second through-via (Fig 9 through hole OP2, [0126]) electrically connected ([0168]) to the first semiconductor chip (Fig 9 display driving circuit 40, [0150]); and a conductive pad (Fig 9 signal line 143, [0168]) on the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the conductive pad (Fig 9 signal line 143, [0168]) electrically connecting ([0170]) the second through-via (Fig 9 through hole OP2, [0126]) and the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) to each other.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the closest art is Lee et.al. (US 20210249627 A1), hereinafter Lee.
Lee teaches a second through-via (Fig 9 through hole OP2, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the second through-via (Fig 9 through hole OP2, [0126]) spaced apart from (Fig 9) the first through-via (Fig 9 through hole OP1, [0126]) in the first horizontal direction (Fig 9 direction DR2), the second through-via (Fig 9 through hole OP2, [0126]) electrically connected ([0168]) to the first semiconductor chip (Fig 9 display driving circuit 40, [0150]); and a conductive pad (Fig 9 signal line 143, [0168]) on the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the conductive pad (Fig 9 signal line 143, [0168]) electrically connecting ([0170]) the second through-via (Fig 9 through hole OP2, [0126]) and the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) to each other.
Lee fails to teach a second through-via in the non-display region.
Claim 20 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 20, the closest art is Lee et.al. (US 20210249627 A1), hereinafter Lee, in view of Lim et.al. (US 20190122943 A1), hereinafter Lim.
Lee teaches a display device (Fig 1 display device 1, [0056]) comprising: a substrate (Fig 9 substrate 110, [0122]) including a display region (See annotated figure; Examiner interprets the display region as shown) and a non-display region (See annotated figure; Examiner interprets the non-display region as shown) adjacent to the display region (See annotated figure) in a horizontal direction (Fig 9 direction DR2), the substrate (Fig 9 substrate 110, [0122]) including silicon (Si) (glass is SiO2, [0125]); a light-emitting element layer (Fig 9 light emitting layer EML, [0122]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) being in the display region (See annotated figure); an upper substrate (Fig 9 encapsulation substrate 20, [0171]) on the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) in the display region (See annotated figure); a thin-film substrate (Fig 9 circuit board 60, [0150]) in (Examiner notes the limitation does not require the entirety of the thin-film substrate to be in the non-display region) the non-display region (See annotated figure), one end of the thin-film substrate (Fig 9 circuit board 60, [0150]) connected to the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]); a semiconductor chip (Fig 9 display driving circuit 40, [0150]) on a lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), at least a portion of the semiconductor chip (Fig 9 display driving circuit 40, [0150]) overlapping with (See annotated figure; left shaded area) the thin-film substrate (Fig 9 circuit board 60, [0150]) in a vertical direction (Fig 9 direction DR3); a molding layer (Fig 9 under-panel member 50, [0079]) on the lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the molding layer (Fig 9 under-panel member 50, [0079]) surrounding a sidewall (Fig 9) of the semiconductor chip (Fig 9 display driving circuit 40, [0150]), a lower surface of the molding layer (Fig 9 under-panel member 50, [0079]) being coplanar with (the thickness of the under-panel member is the same as the driving circuit 40, [0080]) a lower surface of the semiconductor chip (Fig 9 display driving circuit 40, [0150]), a sidewall of the molding layer (Fig 9 under-panel member 50, [0079]) aligned with (See annotated figure; right shaded area) a sidewall of the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3); a first through-via (Fig 9 through hole OP1, [0126]) in the non-display region (Fig 9 non-display area NDA, [0121]), the first through-via (Fig 9 through hole OP1, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the first through-via (Fig 9 through hole OP1, [0126]) electrically connecting ([0150]) the thin-film substrate (Fig 9 circuit board 60, [0150]) and the semiconductor chip (Fig 9 display driving circuit 40, [0150]) to each other; a second through-via (Fig 9 through hole OP2, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the second through-via (Fig 9 through hole OP2, [0126]) spaced apart from the first through-via (Fig 9 through hole OP1, [0126]) in the horizontal direction (Fig 9 direction DR2), the second through-via (Fig 9 through hole OP2, [0126]) electrically connected ([0168]) to the semiconductor chip (Fig 9 display driving circuit 40, [0150]); a conductive pad (Fig 9 signal line 143, [0168]) on the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the conductive pad (Fig 9 signal line 143, [0168]) electrically connecting ([0170]) the second through-via (Fig 9 through hole OP2, [0126]) and the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) to each other; and a partitioning wall (Fig 9 sealing member 30, [0134]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the partitioning wall (Fig 9 sealing member 30, [0134]) being in the display region (See annotated figure), the partitioning wall (Fig 9 sealing member 30, [0134]) surrounding a sidewall (Fig 9) of the light-emitting layer (Fig 9 light emitting layer EML, [0122]).
Lee fails to teach a circuit board connected to an opposite end of the thin-film substrate.
However, Lim teaches a circuit board (Fig 17 printed circuit 300, [0139]) connected to an opposite end (end not connected to display panel 400 corresponds to Lee: end not connected to pad PD) of the thin-film substrate (Fig 17 semiconductor package 100, [0139] corresponds to Lee: Fig 9 circuit board 60, [0150]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teachings of Lim by having a circuit board connected to an opposite end of the thin-film substrate. This enables the communication of the display area with other components of the display device ([0135]).
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Lee and Lim fail to teach a second through-via in the non-display region.
Response to Arguments
Applicant’s arguments, see 35 USC §102 section on page 10, filed My 27, 2026, with respect to amendments to independent claims 1 and 13 have been fully considered but they are not persuasive.
Examiner notes, as outlined in the rejection above, that the display region and non-display regions as written were interpreted by Examiner to be different. In doing so a portion of the partition wall would be in the display region, the limitation not requiring the entirety of any particular part to be in one region or another.
Applicant’s arguments, see 35 USC §103 section on page 11, filed My 27, 2026, with respect to amendments to claim 20 have been fully considered and are persuasive. The 35 USC §103 rejection of claim 20 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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