DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of Species A in the reply filed on December 29, 2025 is acknowledged. The traversal is on the ground(s) that there is substantial overlap and additional species would be found during searching. This is not found persuasive because there is no guarantee that additional species would be found during searching so the burden of search for other species is still present.
The requirement is still deemed proper and is therefore made FINAL.
Claims 6, 8-12, and 15-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on December 29, 2025.
Claim Objections
Claim 14 is objected to because of the following informalities:
Claim 14 line 2 appears to be missing a word “a second through-via extending the substrate” Examiner interprets the limitation to read “a second through-via extending through the substrate.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et.al. (US 20210249627 A1), hereinafter Lee.
Regarding claim 1, Lee teaches a display device (Fig 1 display device 1, [0056]) comprising: a substrate (Fig 9 substrate 110, [0122]) including a display region (Fig 9 display area DA, [0121]) and a non-display region (Fig 9 non-display area NDA, [0121]) adjacent to the display region (Fig 9 display area DA, [0121]) in a first horizontal direction (Fig 9 direction DR2); a light-emitting element layer (Fig 9 light emitting layer EML, [0122]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]) in the display region (Fig 9 display area DA, [0121]); a thin-film substrate (Fig 9 circuit board 60, [0150]) connected to the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]) in the non-display region (Fig 9 non-display area NDA, [0121]); a first semiconductor chip (Fig 9 display driving circuit 40, [0150]) on a lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), at least a portion of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) overlapping (See annotated figure; shaded area) with the thin-film substrate (Fig 9 circuit board 60, [0150]) in a vertical direction (Fig 9 direction DR3); and a first through-via (Fig 9 through hole OP1, [0126]) in the non-display region (Fig 9 non-display area NDA, [0121]), the first through-via (Fig 9 through hole OP1, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the first through-via (Fig 9 through hole OP1, [0126]) electrically connecting ([0150]) the thin-film substrate (Fig 9 circuit board 60, [0150]) and the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) to each other.
PNG
media_image1.png
508
672
media_image1.png
Greyscale
Regarding claim 2, Lee teaches the substrate (Fig 9 substrate 110, [0122]) includes silicon (Si) (glass is SiO2, [0125]).
Regarding claim 3, Lee teaches a molding layer (Fig 9 under-panel member 50, [0079]) on the lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the molding layer (Fig 9 under-panel member 50, [0079]) surrounding a sidewall (Fig 9) of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]).
Regarding claim 4, Yang teaches a sidewall of the substrate (Fig 9 substrate 110, [0122]) is aligned (See annotated figure; shaded area) with a sidewall of the molding layer (Fig 9 under-panel member 50, [0079]) in the vertical direction (Fig 9 direction DR3).
PNG
media_image2.png
508
672
media_image2.png
Greyscale
Regarding claim 5, Lee teaches a lower surface of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) is coplanar (the thickness of the under-panel member is the same as the driving circuit 40, [0080]) with a lower surface of the molding layer (Fig 9 under-panel member 50, [0079]).
Regarding claim 7, Lee teaches a second through-via (Fig 9 through hole OP2, [0126]) in the non-display region (Fig 9 non-display area NDA, [0121]), the second through-via (Fig 9 through hole OP2, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the second through-via (Fig 9 through hole OP2, [0126]) spaced apart from (Fig 9) the first through-via (Fig 9 through hole OP1, [0126]) in the first horizontal direction (Fig 9 direction DR2), the second through-via (Fig 9 through hole OP2, [0126]) electrically connected ([0168]) to the first semiconductor chip (Fig 9 display driving circuit 40, [0150]); and a conductive pad (Fig 9 signal line 143, [0168]) on the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the conductive pad (Fig 9 signal line 143, [0168]) electrically connecting ([0170]) the second through-via (Fig 9 through hole OP2, [0126]) and the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) to each other.
Regarding claim 13, Lee teaches a display device (Fig 1 display device 1, [0056]) comprising: a substrate (Fig 9 substrate 110, [0122]) including silicon (Si) (glass is SiO2, [0125]); a light-emitting element layer (Fig 9 light emitting layer EML, [0122]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]); a thin-film substrate (Fig 9 circuit board 60, [0150]) connected to the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the thin-film substrate (Fig 9 circuit board 60, [0150]) spaced apart from (Fig 9) the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) in a horizontal direction (Fig 9 direction DR2); a first semiconductor chip (Fig 9 display driving circuit 40, [0150]) on a lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), at least a portion of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) overlapping with (See annotated figure; shaded area) the thin-film substrate (Fig 9 circuit board 60, [0150]) in a vertical direction (Fig 9 direction DR3); a molding layer (Fig 9 under-panel member 50, [0079]) on the lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the molding layer (Fig 9 under-panel member 50, [0079]) surrounding a sidewall (Fig 9) of the first semiconductor chip (Fig 9 display driving circuit 40, [0150]); and a first through-via (Fig 9 through hole OP1, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the first through-via (Fig 9 through hole OP1, [0126]) electrically connecting ([0150]) the thin-film substrate (Fig 9 circuit board 60, [0150]) and the first semiconductor chip (Fig 9 display driving circuit 40, [0150]) to each other.
PNG
media_image1.png
508
672
media_image1.png
Greyscale
Regarding claim 14, Lee teaches a second through-via (Fig 9 through hole OP2, [0126]) extending the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the second through-via (Fig 9 through hole OP2, [0126]) spaced apart from (Fig 9) the first through-via (Fig 9 through hole OP1, [0126]) in the horizontal direction (Fig 9 direction DR2), the second through-via (Fig 9 through hole OP2, [0126]) electrically connected ([0168]) to the first semiconductor chip (Fig 9 display driving circuit 40, [0150]); and a conductive pad (Fig 9 signal line 143, [0168]) on the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the conductive pad (Fig 9 signal line 143, [0168]) electrically connecting ([0170]) the second through-via (Fig 9 through hole OP2, [0126]) and the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) to each other.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et.al. (US 20210249627 A1), hereinafter Lee, in view of Lim et.al. (US 20190122943 A1), hereinafter Lim.
Lee teaches a display device (Fig 1 display device 1, [0056]) comprising: a substrate (Fig 9 substrate 110, [0122]) including a display region (Fig 9 display area DA, [0121]) and a non-display region (Fig 9 non-display area NDA, [0121]) adjacent to the display region (Fig 9 display area DA, [0121]) in a horizontal direction (Fig 9 direction DR2), the substrate (Fig 9 substrate 110, [0122]) including silicon (Si) (glass is SiO2, [0125]); a light-emitting element layer (Fig 9 light emitting layer EML, [0122]) on an upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]) in the display region (Fig 9 display area DA, [0121]); an upper substrate (Fig 9 encapsulation substrate 20, [0171]) on the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) in the display region (Fig 9 display area DA, [0121]); a thin-film substrate (Fig 9 circuit board 60, [0150]) in the non-display region (Fig 9 non-display area NDA, [0121]), one end of the thin-film substrate (Fig 9 circuit board 60, [0150]) connected to the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]); a semiconductor chip (Fig 9 display driving circuit 40, [0150]) on a lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), at least a portion of the semiconductor chip (Fig 9 display driving circuit 40, [0150]) overlapping with (See annotated figure; left shaded area) the thin-film substrate (Fig 9 circuit board 60, [0150]) in a vertical direction (Fig 9 direction DR3); a molding layer (Fig 9 under-panel member 50, [0079]) on the lower surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the molding layer (Fig 9 under-panel member 50, [0079]) surrounding a sidewall (Fig 9) of the semiconductor chip (Fig 9 display driving circuit 40, [0150]), a lower surface of the molding layer (Fig 9 under-panel member 50, [0079]) being coplanar with (the thickness of the under-panel member is the same as the driving circuit 40, [0080]) a lower surface of the semiconductor chip (Fig 9 display driving circuit 40, [0150]), a sidewall of the molding layer (Fig 9 under-panel member 50, [0079]) aligned with (See annotated figure; right shaded area) a sidewall of the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3); a first through-via (Fig 9 through hole OP1, [0126]) in the non-display region (Fig 9 non-display area NDA, [0121]), the first through-via (Fig 9 through hole OP1, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the first through-via (Fig 9 through hole OP1, [0126]) electrically connecting ([0150]) the thin-film substrate (Fig 9 circuit board 60, [0150]) and the semiconductor chip (Fig 9 display driving circuit 40, [0150]) to each other; a second through-via (Fig 9 through hole OP2, [0126]) in the non-display region (Fig 9 non-display area NDA, [0121]), the second through-via (Fig 9 through hole OP2, [0126]) extending through the substrate (Fig 9 substrate 110, [0122]) in the vertical direction (Fig 9 direction DR3), the second through-via (Fig 9 through hole OP2, [0126]) spaced apart from the first through-via (Fig 9 through hole OP1, [0126]) in the horizontal direction (Fig 9 direction DR2), the second through-via (Fig 9 through hole OP2, [0126]) electrically connected ([0168]) to the semiconductor chip (Fig 9 display driving circuit 40, [0150]); and a conductive pad (Fig 9 signal line 143, [0168]) on the upper surface (Fig 9) of the substrate (Fig 9 substrate 110, [0122]), the conductive pad (Fig 9 signal line 143, [0168]) electrically connecting ([0170]) the second through-via (Fig 9 through hole OP2, [0126]) and the light-emitting element layer (Fig 9 light emitting layer EML, [0122]) to each other.
Lee fails to teach a circuit board connected to an opposite end of the thin-film substrate.
However, Lim teaches a circuit board (Fig 17 printed circuit 300, [0139]) connected to an opposite end (end not connected to display panel 400 corresponds to Lee: end not connected to pad PD) of the thin-film substrate (Fig 17 semiconductor package 100, [0139] corresponds to Lee: Fig 9 circuit board 60, [0150]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teachings of Lim by having a circuit board connected to an opposite end of the thin-film substrate. This enables the communication of the display area with other components of the display device ([0135]).
PNG
media_image3.png
508
672
media_image3.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813