DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Makala et al. (Makala, 2021/0358952 A1).
Regarding claim 1, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising: a substrate (substrate 9); a plurality of insulating layers (insulation layer 31) stacked on an upper surface of the substrate (substrate 9); a plurality of gate electrodes (gate electrode 45) between the plurality of insulating layers (insulation layer 31); a plurality of gate insulating layers (gate insulation layer 56) in contact with corresponding side surfaces of the plurality of gate electrodes (gate electrode 45); a ferroelectric layer (ferroelectric layer 44) in contact with side surfaces of the plurality of insulating layers (insulation layer 31); a plurality of intermediate electrodes (conductive layer 54) between the plurality of gate insulating layers (gate insulation layer 56) and the ferroelectric layer (ferroelectric layer 44); and a channel layer ( channel layer 60) in contact with the ferroelectric layer (ferroelectric layer 44).
Regarding claim 2, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein each of the plurality of intermediate electrodes (conductive layer 54) is configured to include a charge of a first polarity (see FIG. 17A-B and [0080-0115]).
Regarding claim 3, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein in a cross-sectional view, the plurality of gate electrodes (gate electrode 45) are stacked in a direction perpendicular to the upper surface of the substrate (substrate 9), and each of the plurality of gate electrodes extends in a direction parallel to the upper surface of the substrate (substrate 9).
Regarding claim 4, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein each of the plurality of gate electrodes (gate electrode 45) is electrically connected to a word line [0042]), and each of the plurality of intermediate electrodes are configured (underline limitation considered as product by process) to be a floating electrode.
Regarding claim 5, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the plurality of intermediate electrodes extend to protrude from side surfaces of the plurality of insulating layers (insulation layer 31) in a first direction parallel to the upper surface of the substrate (substrate 9).
Regarding claim 6, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the ferroelectric layer (ferroelectric layer 44) and the channel layer ( channel layer 60) each have a protruding shape corresponding to a protruding portion of the plurality of intermediate electrodes (see FIG. 17A-B).
Regarding claim 7, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the plurality of gate insulating layers (gate insulation layer 56) are respectively on an upper surface, a lower surface, and a side surface of corresponding gate electrodes of the plurality of gate electrodes (gate electrode 45), the upper and lower surfaces of the corresponding gate electrodes parallel to the upper surface of the substrate, and the side surface of the corresponding gate electrodes perpendicular to upper surface the substrate (substrate 9).
Regarding claim 8, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the plurality of gate insulating layers (gate insulation layer 56) are respectively on one side surface of corresponding gate electrodes (gate electrode 45) of the plurality of gate electrodes (see FIG. 17A-B).
Regarding claim 9, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein a source electrode and a drain electrode ([0133-0134]) are respectively on both sides of the channel layer (channel layer 60) in a second direction that is parallel to the substrate and perpendicular to the first direction (see FIG. 17A/B).
Regarding claim 10, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the source electrode is electrically connected to a corresponding source line ([0148]), and the drain electrode is electrically connected to a corresponding bit line ([0148]).
Regarding claim 11, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein in a cross-sectional view, the plurality of intermediate electrodes extend towards side surfaces of the plurality of insulating layers ( insulation layer 31) in a first direction parallel to the upper surface the substrate (substrate 9).
Regarding claim 12, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the plurality of gate insulating layers (gate insulation layer 56) are respectively on an upper surface, a lower surface, and the side surface of corresponding gate electrodes (gate electrode 45) of the plurality of gate electrodes, the upper and lower surfaces of the corresponding gate electrodes parallel to the upper surface of the substrate, and the side surface of the corresponding gate electrodes being perpendicular to the upper surface of the substrate (substrate 9).
Regarding claims 13 and 17, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the plurality of gate insulating layers (gate insulation layer 56) are respectively on the side surface of the corresponding gate electrodes (gate electrode 45).
Regarding claim 14, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein each of the plurality of gate electrodes and each of the plurality of intermediate electrodes independently include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, or polysilicon ([0111]+)
Regarding claim 15, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the insulating layers comprise at least one of SiO, SiOC, SiON, or SiN ([0113]).
Regarding claim 16, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the ferroelectric layers comprise at least one of a ferroelectric fluorite-based material, a ferroelectric nitride-based material, or a ferroelectric perovskite ([0134]).
Regarding claim 18, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the channel layer is provided to correspond with the plurality of gate electrodes (gate electrode 45).
Regarding claim 19, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the channel layer comprises at least one of a Group IV semiconductor, a Group III-V semiconductor, an oxide ( channel layer 60) semiconductor, a nitride semiconductor, a nitrogen oxide semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, or an organic semiconductor ([0115] +).
Regarding claim 20, Makala shows a three-dimensional (3D) ferroelectric memory device (Fig. 17A-B) comprising, wherein the channel layer (channel layer 60) extends in a direction perpendicular to the upper surface of the substrate (substrate 9).
Conclusion
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893